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| FLEX TM ROAMING DECODER II S5T8701 INTRODUCTION 32-LQFP-0707 This FLEX Roaming Decoder II date sheet describes the operation of the S5T8701. The S5T8701 simplifies implementation of a FLEXTM paging device by interfacing with any of several off-the-shelf paging receivers and any of several off-the-shelf host microcontroller/microprocessors. Its primary function is to process information received and demodulated from a FLEX radio paging channel, select messages addressed to the paging device and communicate the message information to the host. The S5T8701 also operates the paging receiver in an efficient power consumption mode and enables the host to operate in a low power mode when monitoring a signal channel for message information. TM FEATURES * * * * * * * * * * * * * * * * * * * * * * * FLEXTM paging protocol decoder 16 programmable user address words 16 fixed temporary addresses 16 operator messaging addresses 1600,3200,and 6400bps(bits per second) decoding Any-phase or single-phase decoding Uses standard Serial Peripheral Interface (SPI) in slave mode Allow low current STOP mode operation of host processor Highly programmable receiver control Real time clock time base FLEX fragmentation and group messaging support Real time clock over-the-air update support Compatible with synthesized receivers SSID and NID Roaming support Low Battery Indication(External detector) 28 used pins (32-pin package standard) Backward compatible to the standard and roaming FLEX decoder ICs Internal demodulator and data slicer Improved battery savings via partial correlation and intermittent receiver clock Full support for revision 1.9 of the FLEX protocol 32-pin LQFP package Supply voltage: 1.8 to 3.6V Operating Frequency: 76.8kHz or 160kHz 1 S5T8701 FLEX TM ROAMING DECODER II ORDERING INFORMATION Device Name S5T8701X01-E0R0 Package Type 32-LQFP-0707 Operating Temperature -25C to 85C 2 FLEX TM ROAMING DECODER II S5T8701 SYSTEM BLOCK DIAGRAM Synthesizer Programming Control Receiver Receiver Control S0/IFIN S5T8701 160 kHz 10 M Host Microprocessor 38.4 or 40kHz Clock 15pF User Interface Low Battery Detector LOBAT 15pF Figure 1 : Example Block Diagram Using Internal Demodulator When configured to use the internal demodulator, the S5T8701 connects to a receiver capable of generating a limited (i.e. 1-bit digitized) 455kHz or 140kHz IF signal. In this mode, the S5T8701 has 7 receiver control lines used for warming up and shutting down a receiver in stages. The S5T8701 has the ability to detect a low battery signal during the receiver control sequences. It interfaces to a host MCU through a standard SPI. It has a 1minute timer that offers low power support for a time of day function on the host. When using the internal demodulator, the oscillator frequency (or external clock) must be 160kHz. The CLKOUT signal can be programmed to be either a 38.4kHz signal created by fractionally dividing the oscillator clock, or a 40kHz signal creating by dividing the oscillator clock by 4. 3 S5T8701 FLEX TM ROAMING DECODER II Synthesizer Programming Control Receiver Audio Audio to Digital Converter EXTS1 EXTS0 S5T8701 76.8 kHz 10 M Receiver Control Host Microprocessor 38.4kHz Clock 10pF User Interface Low Battery Detector LOBAT 10pF Figure 2 : Example Block Diagram Using External Demodulator The S5T8701 can also be configured to connect to a receiver capable of converting a 4 level audio signal into a 2 bit digital signal. In this mode, the S5T8701 has a 8 receiver control lines used for warming up and shutting down a receiver in stages. It also includes configuration setting for the two post detection filter bandwidths required to decode the two symbol rates of the FLEX signal. Also when using an external demodulator, the oscillator frequency (or external clock) must be 76.8kHz and the CLKOUT signal (when enabled) is 38.4kHz clock output capable of driving other devices. 4 FLEX TM ROAMING DECODER II S5T8701 FUNCTIONAL BLOCK DIAGRAM S0-S77 S1-S7 S0 Receiver Control Control/ Demodulator S0/IFIN IFIN & Data Slicer Status Registers 2 VDD 2 VSS EXTS0 EXTS1 SYMCLK OSCPD XTAL EXTAL 76.8 kHz or 160 kHz Oscillator Sync Correlator External Control Unit Symbol Sync Noise Detector TEST2 TEST3 RESET LOBAT CLKOUT Clock Generator Deinterleaver Error Corrector Address Comparator/ Correlator Local Message Filter Control/ Status Registers READY SPI 4 SPI SPI Buffer Figure 3 : Block Diagram 5 S5T8701 FLEX TM ROAMING DECODER II PIN DESCRIPTION PIN NAME VDD VSS LOBAT RESET EXTS1 EXTS0 SS SCK MOSI MISO READY CLKOUT SYMCLK EXTAL XTAL OSCPD PIN 3,13 7,29 10 24 I I TYPE Power Power Ground Low battery detect input Reset Active low reset to the S5T8701. External Symbol Input Signals 11 12 27 28 30 31 26 I I I I I O O MSb of the symbol currently being decoded LSb of the symbol currently being decoded SPI Signals Slave Select for SPI communications Serial Clock for SPI communications Data input for SPI communications Three-state data output for SPI communications Driven low when the IC is ready for an SPI packet Clock Signals 32 14 6 5 2 O O I O I 38.4kHz or 40kHz clock output(derived from oscillator) Recovered symbol clock 76.8kHz or 160kHz crystal input or external input 76.8kHz or 160kHz clock output Internal oscillator power down. Connected to VSS when using internal oscillator. Connected to VDD when using an external source. Receiver Control Lines S1 - S7 S0 / IFIN 22,21,20,1 9,18,16,15 23 O O/I Seven three-state receiver control output S0 : Receiver control output when using external demodulator IFIN : Limited IF input when using internal demodulator Test pins TEST2, TEST3 NC 4,8 1,9,17,25 I O IC manufacturing test mode pin. Normally connected to VSS. IC manufacturing test mode pin. Normally connected to VSS. (Can be left unconnected.) DESCRIPTION 6 FLEX TM ROAMING DECODER II S5T8701 PIN CONFIGURATION 24 23 22 21 20 19 18 17 NC READY SS SCK VSS MOSI MISO CLKOUT 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 RESET S0/IFIN S1 S2 S3 S4 S5 NC S5T8701 S6 S7 SYMCLK VDD EXT0 EXT1 LOBAT NC Figure 4 : S5T8701 32-LQFP Top View NC OSCPD VDD TEST2 XTAL EXTAL VSS TEST3 1 2 3 4 5 6 7 8 7 S5T8701 FLEX TM ROAMING DECODER II SPI PACKETS All data communicated between the S5T8701 and the host MCU is transmitted on the SPI in 32-bit packets. Each packet consists of an 8-bit ID followed by 24 bits of information. The S5T8701 uses the SPI bus in full duplex mode. In other words, whenever a packet communication occurs, the data in both directions is valid packet data. The SPI interface consists of a READY pin and four SPI pins (SS SCK, MOSI, and MISO). The SS is used as a SS, chip select for the S5T8701. The SCK is a clock supplied by the host MCU. The data from the host is transmitted on the MOSI(Master-Out-Slave-In) line. The data from the S5T8701 is transmitted on the MISO(Master-In-SlaveOut) line. Timing requirements for SPI communication are specified in "SPI Timing" on page 69. Packet Communication Initiated by the Host Refer to figure 6 on page 11. When the host sends a packet to the S5T8701, it performs the following steps: 1. 2. 3. 4. 5. Select the S5T8701 by driving the SS pin low. Wait for the S5T8701 to drive the READY pin low. Send the 32-bit packet. De-select the S5T8701 by driving the SS pin high. Repeat steps 1 through 4 for each additional packet. SS READY SCK MOSI MISO 1 2 3 D31 D31 D1 D1 4 D0 D0 D31 D31 D1 D1 D0 D0 D31 D31 D1 D1 D0 D0 High-impedance State Figure 6: Typical Multiple Packet Communications Initiated by the Host When the host sends a packet, it will also receive a valid packet from the S5T8701. If the S5T8701 is enabled (see "Checksum Packet" on page 16 for a definition of enabled) and has no other packets waiting to be sent, the S5T8701 will send a status packet. The host must transition the SS pin from high to low to begin each 32-bit packet. The S5T8701 must see a negative transition on the SS pin in order for the host to initiate each packet communication. 8 FLEX TM ROAMING DECODER II S5T8701 PACKET COMMUNICATION INITIATED BY THE FLEX DECODER IC Refer to figure 7 on page 12. When the S5T8701 has a packet for the host to read, the following occurs: 1. 2. 3. 4. The S5T8701 drives the READY pin low. If the S5T8701 is not already selected, the host selects the S5T8701 by driving the SS pin low. The host receives (and sends) a 32-bit packet. The host de-selects the S5T8701 by driving the SS pin high (optional). SS READY SCK MOSI MISO 1 2 4 3 D31 D31 D1 D1 D0 D0 D31 D31 D1 D1 D0 D0 D31 D31 D1 D1 D0 D0 High-impedance State Figure 7: Typical Multiple Packet Communications Initiated by the FLEX decoder IC When the host is reading a packet from the S5T8701, it must send a valid packet to the S5T8701. If the host has no data to send, it is suggested that the host send a Checksum Packet with all of the data bits set to 0 in order to avoid disabling the S5T8701. See "Checksum Packet" on page 16 for more details on enabling and disabling the S5T8701. The following figure illustrates that it is not necessary to de-select the S5T8701 between packets then the packets are initiated by the S5T8701. SS READY SCK MOSI MISO D31 D31 D1 D1 D0 D0 D31 D31 D1 D1 D0 D0 D31 D31 D1 D1 D0 D0 High-impedance State Figure 8: Multiple Packet Communications Initiated by the FLEX decoder IC with No De-select 9 S5T8701 FLEX TM ROAMING DECODER II HOST-TO-DECODER PACKET MAP The upper 8 bits of a packet comprise the packet ID. The following table describes the packet id's for all of the packets that can be sent to the S5T8701 from the host. Table 1: Host-to-Decoder Packet ID Map Packet ID (Hexadecimal) 00 01 02 03 04 05 06 07 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1F 20 21 22 23 24 25 26 Checksum Configuration Control All Frame Mode Operator Message Address Enables Roaming Control Packet Timing Control Packet Reserved (Host should never send) Receiver Line Control Receiver Control Configuration (Off setting) Receiver Control Configuration (Warm Up 1 Setting) Receiver Control Configuration (Warm Up 2 Setting) Receiver Control Configuration (Warm Up 3 Setting) Receiver Control Configuration (Warm Up 4 Setting) Receiver Control Configuration (Warm Up 5 Setting) Receiver Control Configuration (3200sps Sync Setting) Receiver Control Configuration (1600sps Sync Setting) Receiver Control Configuration (3200sps Data Setting) Receiver Control Configuration (1600sps Data Setting) Receiver Control Configuration (Shut Down 1 Setting) Receiver Control Configuration (Shut Down 2 Setting) Special (Ignored by S5T8701) Frame-Assignment (Frames 112 through 127) Frame Assignment (Frames 96 through 111) Frame Assignment (Frames 80 through 95) Frame Assignment (Frames 64 through 79) Frame Assignment (Frames 48 through 63) Frame Assignment (Frames 32 through 47) Frame Assignment (Frames 16 through 31) 35 35 35 35 35 35 35 29 30 31 31 31 31 31 32 33 33 33 34 34 Packet Type Page 16 18 21 23 24 25 28 10 FLEX TM ROAMING DECODER II S5T8701 Table 1: Host-to-Decoder Packet ID Map (Continued) Packet ID (Hexadecimal) 27 28 77 78 79 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 FF Packet Type Frame Assignment (Frames 0 through 15) Reserved (Host should never send) User Address Enable Reserved (Host should never send) User Address Assignment (User address 0) User Address Assignment (User address 1) User Address Assignment (User address 2) User Address Assignment (User address 3) User Address Assignment (User address 4) User Address Assignment (User address 5) User Address Assignment (User address 6) User Address Assignment (User address 7) User Address Assignment (User address 8) User Address Assignment (User address 9). User Address Assignment (User address 10) User Address Assignment (User address 11) User Address Assignment (User address 12) User Address Assignment (User address 13) User Address Assignment (User address 14) User Address Assignment (User address 15) Reserved (Host should never send) 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 36 Page 35 11 S5T8701 FLEX TM ROAMING DECODER II DECODER-TO-HOST PACKET MAP The following table describes the packet ID's for all of the packets that can be sent to the host from the S5T8701. Table 2: Decoder-to-Host Packet ID Map Packet ID (Hexadecimal) 00 01 02 57 58 5F 60 61 7D 7E 7F 80 FE FF Block Information Word Address Vector or Message (ID is word number in frame) Reserved Roaming Status Packet Reserved Receiver Shutdown Status Reserved Part ID 53 50 51 48 Packet Type Page 39 41 42 12 S5T8701 FLEX TM ROAMING DECODER II HOST-TO-DECODER PACKET DESCRIPTIONS The following sections describe the packets of information sent from the host to the S5T8701. In all cases the packets should be sent MSB first (bit 7 of byte 3 = bit 31 of the packet = MSB). CHECKSUM PACKET The Checksum Packet is used to insure proper communication between the host and the S5T8701. The S5T8701 exclusive-or's the 24 data bits of every packet it receives (except the Checksum Packet and the special packet ID's 1C through 1F hexadecimal) with an internal checksum register. Upon reset and whenever the host writes a packet to the S5T8701, the S5T8701 is disabled from sending any information to the host processor until the host processor sends a Checksum Packet with the proper checksum value (CV) to the S5T8701. When the S5T8701 is disabled in this way, it prompts the host to read the Part ID Packet. Note that all other operation continues normally when the S5T8701 is "disabled". Disabled only implies that data cannot be read, all other internal operations continue to function. When the S5T8701 is reset, it is disabled and the internal checksum register is initialized to the 24 bit part ID defined in the Part ID Packet. See "Part ID Packet" on page 53 for a description of the Part ID. Every time a packet other than the Checksum Packet and the special packets 1C through 1F is sent to the S5T8701, the value sent in the 24 information bits is exclusive-or'ed with the internal checksum register, the result is stored back to the checksum register, and the S5T8701 is disabled. If a Checksum Packet is sent and the CV bits match the bits in the checksum register, the S5T8701 is enabled. If a Checksum Packet is sent when the S5T8701 is already enabled, the packet is ignored by the S5T8701 in which case a null packet having the ID and data bits set to 0 is suggested. If a packet other than the Checksum Packet is sent when the S5T8701 is enabled, the S5T8701 will be disabled until a Checksum Packet is sent with the correct CV bits. When the host reads a packet out of the S5T8701 but has no data to send, the Checksum Packet should be sent so the S5T8701 will not be disabled. The data in the Checksum Packet could be a null packet (32 bit stream of all zeros) since a Checksum Packet will not disable the S5T8701. When the host re-configures the S5T8701, the S5T8701 will be disabled from sending any packets other than the Part ID Packet until the S5T8701 is enabled with a Checksum Packet having the proper data. The ID of the Checksum Packet is 0. Table 3: Checksum Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 CV: 0 CV23 CV15 CV7 Checksum Value. Bit 6 0 CV22 CV14 CV6 Bit 5 0 CV21 CV13 CV5 Bit 4 0 CV20 CV12 CV4 Bit 3 0 CV19 CV11 CV3 Bit 2 0. CV18 CV10 CV2 Bit 1 0 CV17 CV9 CV1 Bit 0 0 CV16 CV8 CV0 13 FLEX TM ROAMING DECODER II S5T8701 RESET Decoder disables itself Decoder initializes checksum register to Part ID value Decoder initiates Pare ID packet Decoder waits for SPI packet from host Y Y Checksum packet? N Decoder enabled? N Packet data matches checksum register data? Decoder disables itself N Y Decoder enables itself Decoder sets checksum register to the XOR of the packet data bits with the checksum register bits Figure 9: FLEX Decoder IC Checksum Flow Chart 14 S5T8701 FLEX TM ROAMING DECODER II CONFIGURATION PACKET The Configuration Packet defines a number of different configuration options for the S5T8701. Proper operation is not guaranteed if these settings are changed when decoding is enabled (i.e. the ON bit in the Control Packet is set). The ID of the Configuration Packet is 1. Table 4: Configuration Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 DFC: 0 0 0 SME Bit 6 0 DFC 0 MOT Bit 5 0 0 0 COD Bit 4 0 0 0 MTE Bit 3 0 0 0 LBP Bit 2 0 IDE PCE ICO Bit 1 0 OFD1 SP1 0 Bit 0 1 OFD0 SP0 0 Disable Fractional Clock. When this bit is set and IDE is set, the CLKOUT signal will generate a 40kHz signal (EXTAL divided by 4). When this bit is cleared and IDE is set, the CLKOUT signal will generate 38.4kHz signal (EXTAL fractionally divided by 25/6 see diagram below). This bit has no effect when IDE is cleared. (value after reset=0) EXTAL CLKOUT w/DFC=1 CLKOUT w/DFC=0 IDE: Internal Demodulator Enable. When this bit is set , the internal demodulator is enabled and clock frequency at EXTAL is expected to be 160kHz. When this bit is cleared, the internal demodulator is disabled and the clock frequency at EXTAL is expected to be 76.8kHz.(value after reset=0) 15 FLEX TM ROAMING DECODER II S5T8701 OFD: Oscillator Frequency Difference. These bits describe the maximum difference in the frequency of the 76.8kHz oscillator crystal with respect to the frequency of the transmitter. These limits should be the worst case difference in frequency due to all conditions including but not limited to aging, temperature, and manufacturing tolerance. Using a smaller frequency difference in this packet will result in lower power consumption due to higher receiver battery save ratios. Note that this value is not the absolute error of the oscillator frequency provided to the S5T8701. The absolute error of the clock used by the FLEX transmitter must be taken into account. (e.g. If the transmitter tolerance is 25ppm and the 76.8kHz oscillator tolerance is 140ppm, the oscillator frequency difference is 65ppm and OFD should be set to 0.)(value after reset=0) OFD1 0 0 1 1 OFD0 0 1 0 1 Frequency Difference 300ppm 150ppm 75ppm 0ppm PCE: Partial Correlation Enable. When this bit is set, partial correlation of addresses is enabled. When partial correlation is enabled, the S5T8701 will shutdown the receiver before the end of the last FLEX block which contains addresses if it can determine that none of the addresses in that FLEX block will match any enabled address in the S5T8701. When this bit is cleared, the receiver will be controlled as it was in previous versions of the IC.(value after reset=0) Signal Polarity. These bits set the polarity of EXTS1 and EXTS0 input signals. (value after reset=0) The polarity of the EXTS0 and EXTS1 bits will be determined by the receiver design. SP1 0 0 1 1 SP0 0 1 0 1 Signal Polarity EXTS1 EXTS0 Normal Normal Inverted Inverted Normal Inverted Normal Inverted FSK Modulation @SP = 0, 0 +4800Hz +1600Hz -1600Hz -4800Hz EXTS1 1 1 0 0 EXTS0 0 1 1 0 SP: SME: Synchronous Mode Enable. When this bit is set, a Status Packet will be automatically sent whenever the SMU (synchronous mode update) bit in the Status Packet is set. The host can use the SM (synchronous mode) bit in the Status Packet as an in-range/out-of-range indication. (value after reset=0) Maximum Off Time. This bit has no effect if AST in the Timing Control Packet is non-zero. When AST=0 and MOT=0, asynchronous A-word searches will time-out in 4 minutes. When AST=0 and MOT=1, asynchronous A-word searches will time-out in 1 minute. (value after reset=0) MOT: 16 S5T8701 FLEX TM ROAMING DECODER II COD: Clock Output Disable. When this bit is clear, a 38.4kHz or 40kHz(depending on IDE and DFC) signal will be output on the CLKOUT pin. When this bit is set, the CLKOUT pin will be driven low. Note that setting and clearing this bit can cause pulses on the CLKOUT pin that are less than one half the clock period. Also note that when the clock output is enabled and not set for clock intermittent operation(see ICO in this packet), the CLKOUT pin will always output the clock signal even when the S5T8701 is in reset (as long as the S5T8701 oscillator is seeing clocks). Further note that the when the S5T8701 is used in internal demodulator mode(i.e. uses a 160kHz oscillator), the CLKOUT pin will be 80kHz from reset until the time the IDE bit is set. This is because the S5T8701 defaults to external demodulator mode at reset. (value after reset=0) Minute Timer Enable. When this bit is set, a Status Packet will be sent at one minute intervals with the MT (minute time-out) bit in the Status Packet set. When this bit is clear, the internal one-minute timer stops counting. The internal one-minute timer is reset when this bit is changed from 0 to 1 or when the MTC (minute timer clear) bit in the Control Packet is set. Note that the minute timer will not be accurate using a 160kHz oscillator until the IDE bit is set. (value after reset=0) Low Battery Polarity. This bit defines the polarity of the S5T8701's LOBAT pin. The LB bit in the Status Packet is initialized to the inverse value of this bit when the S5T8701 is turned on (by setting the ON bit in the Control Packet). When the S5T8701 is turned on, the first low battery update in the Status Packet will be sent to the host when a low battery condition is detected on the LOBAT pin. Setting this bit means that a high on the LOBAT pin indicates a low voltage condition. (value after reset=0) Intermittent Clock Out. When this bit is clear and COD is clear, a 38.4kHz or 40kHz (depending on the values of IDE and DFC) signal will be output on the CLKOUT pin. When this bit is set and COD is clear, the clock will only be output on the CLKOUT pin while the receiver is not in the Off state. The clock will be output for a few cycles before the receiver transitions from the off state and for a few cycles after the receiver transitions to the off state (this is to insure that the receiver receives enough clocks to detect and process the changes to and from the Off state). The CLKOUT pin will be driven low when it is not driving a clock. Note that when the clock is automatically enabled and disabled (i.e. when ICO is set), the CLKOUT signal transitions will be clean(i.e. no pulses less than half the clock period) when it transitions between no clock and clocked output. This bit has no effect when COD is set. (value after reset=0) MTE: LBP: ICO: 17 FLEX TM ROAMING DECODER II S5T8701 CONTROL PACKET The Control Packet defines a number of different control bits for the S5T8701. The ID of the Control Packet is 2. Table 5: Control Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 FF7 0 0 Bit 6 0 FF6 SPM SBI Bit 5 0 FF5 PS1 0 Bit 4 0 FF4 PS0 MTC Bit 3 0 FF3 0 0 Bit 2 0 FF2 0 0 Bit 1 1 FF1 0 EAE Bit 0 0 FF0 0 ON FF: Force Frame 0-7. These bits enable and disable forcing the S5T8701 to look in frames 0 through 7. When an FF bit is set, the S5T8701 will decode the corresponding frame. Unlike the AF bits in the Frame Assignment Packets, the system collapse of a FLEX system will not affect frames assigned using the FF bits (e.g. Where as setting AF0 to 1 when the system collapse is 5 will cause the S5T8701 to decode frames 0, 32, 64, and 96, setting FF0 to 1 when the system collapse is 5 will only cause the S5T8701 to decode frame 0.). This may be useful for acquiring transmitted time information or channel attributes (e.g. Local ID). (value after reset =0) Single Phase Mode. When this bit is set, the S5T8701 will decode only one phase of the transmitted data. When this bit is clear, the S5T8701 will decode all of the phases it receives. A change to this bit while the S5T8701 is on, will not take affect until the next block 0 of the next decoded frame. (value after reset =0) Phase Select. When the SPM bit is set, these bits define what phase the S5T8701 should decode according to the following table. This value is determined by the service provider. A change to these bits while the S5T8701 is on, will not take affect until the next block 0 of a frame. (value after reset =0) PS Value PS1 0 0 1 1 PS0 0 1 0 1 Phase Decoded (based on FLEX Data Rate) 1600bps a a a a 3200bps a a c c 6400bps a b c d SPM: PS: SBI: Send Block Information words 2-4. When this bit is set, any errored or time related block information words 2-4 will be sent to the host. See "Block Information Word Packet" on page39 for a description of the words sent. (value after reset=0) Minute Timer Clear. Setting this bit will cause the one minute timer to restart from 0. MTC: 18 S5T8701 FLEX TM ROAMING DECODER II EAE: End of Addresses Enable. When this bit is set, the EA bit in the Status Packet will be set immediately after the S5T8701 decodes the last address word in the frame if there was any address detected in the frame. When this bit is cleared, the EA bit will never be set. Turn On Decoder. Set if the S5T8701 should be decoding FLEX signals. Clear if signal processing should be off (very low power mode). If the ON bit is changed twice and the control packets making the changes are received within 2ms of each other, the S5T8701 may ignore the double change and stay in its original state (e.g. if it is turned off then on again within 2ms it may stay on and ignore the off pulse). Therefore it is recommended that the host insures a minimum of 2ms between changes in the ON bit. (value after reset=0) ON: NOTES: Turning off the S5T8701 must be done using the following sequence. This sequence is performed automatically by the FLEX stack software version 1.2 and greater. 1. Turn off the S5T8701 by sending a Control Packet with the ON bit cleared. 2. Turn on the S5T8701 by sending a Control Packet with the ON bit set. 3. Turn off the S5T8701 by sending a Control Packet with the ON bit cleared. Timing between these steps is specified below and is measured from the positive edge of the last clock of one packet to the positive edge of the last clock of the next packet: * The minimum time between steps 1 and 2 is 2ms or the programmed shut down time, whichever is greater. The programmed shut down time is the sum of all the of the times . programmed in the used Receiver Shut Down Settings Packets. There is no maximum time between steps 1 and 2. The minimum time between steps 2 and 3 is 2ms. The maximum time between steps 2 and 3 is the programmed warm up time minus 2ms. The programmed warm up time is the sum of all the of the times programmed in the used Receiver Warm Up Settings Packets. * * * 19 FLEX TM ROAMING DECODER II S5T8701 ALL FRAME MODE PACKET The All Frame Mode Packet is used to decrement temporary address enable counters by one, decrement the all frame mode counter by one, and/or enable or disable forcing all frame mode. All frame mode is enabled if any temporary address enable counter is non-zero, the all frame mode counter is non-zero, or the force all frame mode bit is set. If all frame mode is enabled, the S5T8701 will attempt to decode every frame and send a Status Packet with the EOF (end-of-frame) bit set at the end of every frame. Both the all frame mode counter and the temporary address enable counters can only be incremented internally by the S5T8701 and can only be decremented by the host. The S5T8701 will increment a temporary address enable counter whenever a short instruction vector is received assigning the corresponding temporary address. See "Operation of a Temporary Address" on page 64 for details. The S5T8701 will increment the all frame mode counter whenever an alphanumeric, HEX / binary, or secure vector is received. When the host determines that a message associated with a temporary address, or a fragmented message has ended, then the appropriate temporary address counter or all frame mode counter should be decremented by writing an All Frame Mode Packet to the S5T8701 in order to exit the all frame mode, thereby improving battery life. See "Building a Fragmented Message" on page 61 for details. Neither the temporary address enable counters nor the all frame mode counter can be incremented past the value 127 (i.e. it will not roll-over) or decremented past the value 0. The temporary address enable counters and the all frame mode counter are initialized to 0 at reset and when the decoder is turned off. The ID of the All Frame Mode Packet is 3. Table 6: All Frame Mode Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 DAF: 0 DAF DTA15 DTA7 Bit 6 0 FAF DTA14 DTA6 Bit 5 0 0 DTA13 DTA5 Bit4 0 0 DTA12 DTA4 Bit 3 0 0 DTA11 DTA3 Bit 2 0 0 DTA10 DTA2 Bit 1 1 0 DTA9 DTA1 Bit 0 1 0 DTA8 DTA0 Decrement All Frame counter. Setting this bit decrements the all frame mode counter by one. If a packet is sent with this bit clear, the all frame mode counter is not affected. (value after reset=0) Force All Frame mode. Setting this bit forces the S5T8701 to enter all frame mode. If this bit is clear, the S5T8701 may or may not be in all frame mode depending on the status of the all frame mode counter and the temporary address enable counters. This may be useful in acquiring transmitted time information.(value after reset=0) Decrement Temporary Address enable counter. When a bit in this word is set, the corresponding temporary address enable counter is decremented by one. When a bit is cleared, the corresponding temporary address enable counter is not affected. When a temporary address enable counter reaches zero, the temporary address is disabled.(value after reset=0) FAF: DTA: 20 S5T8701 FLEX TM ROAMING DECODER II OPERATOR MESSAGING ADDRESS ENABLE PACKET The operator messaging address enable packet is used to enable and disable the built-in FLEX operator messaging addresses. Enabling and disabling operator messaging addresses does not affect what frames the decoder IC decodes. To decode the proper frames, the host must modify the FF bits in the Control Packet or the AF bits in the Frame Assignment Packets. The ID of the operator messaging address enable packet is 4. Table 7: System Address Enable Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 OAE: 0 0 OAE15 OAE7 Bit 6 0 0 OAE14 OAE6 Bit 5 0 0 OAE13 OAE5 Bit4 0 0 OAE12 OAE4 Bit 3 0 0 OAE11 OAE3 Bit 2 1 0 OAE10 OAE2 Bit 1 0 0 OAE9 OAE1 Bit 0 0 0 OAE8 OAE0 Operator messaging Address Enable. When a bit is set, the corresponding operator messaging address is enabled. When it is cleared, the corresponding operator messaging address is disabled. OAE0 through OAE15 corresponds to the hexadecimal operator messaging address values of 1F7810 through 1F781F respectively. (value after reset=0) 21 FLEX TM ROAMING DECODER II S5T8701 ROAMING CONTROL PACKET The roaming control packet controls the features of the S5T8701 that allow implementation of a roaming device. The ID of the roaming control packet is 5. Table 8: Roaming Control Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 IRS: 0 IRS RND 0 Bit 6 0 NBC ABI 0 Bit 5 0 MCM SAS MFC1 Bit4 0 IS1 DAS MFC0 Bit 3 0 SDF 0 0 Bit 2 1 RSP 0 0 Bit 1 0 SND 0 MCO1 Bit 0 1 CND 0 MCO0 Ignore Re-synchronization Signal. When this bit is set, S5T8701 will not go asynchronous when detecting an Ar or Ar signal during searches for A-words. It will merely report that the resynchronization signal was received by setting RSR to 1 in the Roaming Status packet. This allows the host to decide what to do when the paging device is synchronous to more than one channel and only one channel is sending the re-synchronization signal. It also prevents the S5T8701 from losing synchronization when it detects the re-synchronization signal while the paging device is checking an unknown channel. This bit is set and cleared by the host. (value after reset=0) Network Bit Check. Setting this bit will enable reporting of the received network bit value (NBU and n) in the Roaming Status Packet. Setting this bit also makes the S5T8701 abandon a frame after the Frame Info word without synchronizing to the frame if the frame information word is uncorrectable or if the n bit in the frame information word is not set. If the S5T8701 was in synchronous mode when this occurred (probably due to synchronizing to a second channel), it will maintain synchronization to the original channel. If the S5T8701 was in asynchronous mode when this occurred, it will stay in asynchronous mode and end the A-word search. This is done to avoid synchronizing to a non-roaming channel when searching for roaming channels. This bit is set and cleared by the host. (value after reset=0) Manual Collapse Mode. When this bit is set, the S5T8701 behaves as if the system collapse was 7. The S5T8701 will not apply the received system collapse to the AF bits. When this bit is set, the received system collapse is reported to the host via SCU and RSC in the Roaming Status Packet. This is so the host can modify the AF bits based on the system collapse of the channel. This bit is set and cleared by the host. (value after reset=0) Invert EXTS1. Setting this bit inverts the expected polarity of the EXTS1 pin from the way it is configured by SP1 in the Configuration Packet (e.g. if both IS1 and SP1 are set, the polarity of the EXTS1 pin is untouched). This bit is intended to be changed when a change in a channel changes the polarity of the received signal. This bit is set and cleared by the host. This bit has the equivalent effect when using the internal demodulator. (value after reset=0) Stop Decoding Frame. Setting this bit causes the S5T8701 to stop decoding a frame without losing frame synchronization. This bit is set by the host, and cleared by the S5T8701 once it has been processed. The packet with the SDF bit set must be sent after receiving the status packet with EA bit set. It must be sent within 40ms of the end of block in which the S5T8701 set the EA bit. (value after reset=0) NBC: MCM: IS1: SDF: 22 S5T8701 FLEX TM ROAMING DECODER II RSP: Receiver Shutdown Packet enable. When this bit is set, a Receiver Shutdown Packet will be sent whenever the receiver is shut down. The receiver shutdown packet informs the host that the receiver shutdown, and how long it will be before the S5T8701 will automatically warm the receiver back up. (value after reset=0) Start Noise Detect. Setting this bit while the S5T8701 is battery saving will cause it to warm-up the receiver, run a noise detect, and report the result of the noise detect via NDR in the Roaming Status Packet. This bit is set by the host, and cleared by the S5T8701 once it has been processed. If the time comes for the S5T8701 to warm up for automatically or the SAS bit is set while an SND is being processed, the noise detect will be abandoned and the abandoned noise detect result (NDR=01) will be sent in the Roaming Status Packet. (value after reset=0) Continuous Noise Detect. Setting this bit will cause the S5T8701 to do continuous noise detects during the decoded block data of a frame. The results of the noise detect will only be reported if noise is detected (NDR=11). Only one noise detected result (NDR=11) will be sent per block. If the S5T8701 has not completed a noise detect when it shuts down for the frame, that noise detect will be abandoned, but no abandon result (NDR=01) will be sent. This bit is set and cleared by the host. (value after reset=0) Report Noise Detects. Setting this bit will cause the S5T8701 to report the results of the noise detects it does under normal asynchronous operation (when first turned on and when synchronous). The results of the noise detect will be reported via NDR in the Roaming Status acket. This bit is set and cleared by the host. (value after reset=0) All Block Information words. When this bit is set, the S5T8701 will send all received Block information words 2-4 to the host. Note: Setting the SBI bit in the Control Packet only enables errored and real time clock related block info words. (value after reset=0) Start A-word Search. Setting this bit while in asynchronous battery save mode will cause the S5T8701 to warm-up the receiver and run an A-word search. If, during the A-word search, the S5T8701 finds sufficient FLEX signal, it will enter synchronous mode and start decoding the frame. If the A-word search times-out without finding sufficient FLEX signal, it will battery save and continue doing periodic noise detects. The time-out for the A-word searches is controlled by the AST bits in the Timing Control Packet and the MOT bit in the Configuration Packet. The A-word search takes priority over noise detects. Therefore, if the S5T8701 is performing an A-word search and the time comes to do automatic noise detect, the noise detect will not be performed. This bit is set by the host, and cleared by the S5T8701 once it has been acted on. (value after reset=0) Disable A-word Search. When this bit is set, an A-word search will not automatically occur after a noise detect in asynchronous mode finds FLEX signal. This includes automatic noise detects and noise detects initiated by the host by setting SND. The S5T8701 will shut down the receiver after the noise detect completes regardless of the result. When this bit is cleared, A-word searches will occur after a noise detect finds signal in asynchronous mode. (value after reset=0) SND: CND: RND: ABI: SAS: DAS: 23 FLEX TM ROAMING DECODER II S5T8701 MFC: Missed Frame Control. These bits control the frames for which missing frame data (MS1, MFI, MS2, MBI, and MAW) is reported in the Roaming Status Packet. (value after reset=0) MFC1 0 0 1 1 MFC0 0 1 0 1 Missing Frame Data Reported Never Only during frames 0 through 3 Only during frames 0 through 7 Always MCO: Maximum Carry On. The value of these bits sets the maximum carry on that the S5T8701 will follow. For example, if the S5T8701 receives a carry on of 3 over the air and MCO is set to 1, the S5T8701 will only carry on for one frame. (value after reset=3) 24 S5T8701 FLEX TM ROAMING DECODER II TIMING CONTROL PACKET The timing control packet gives the host control of the timing used when the S5T8701 is in asynchronous mode. The packet ID for the timing control packet is 6. Table 9: Timing Control Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 AST7 ABT7 Bit 6 0 0 AST6 ABT6 Bit 5 0 0 AST5 ABT5 Bit4 0 0 AST4 ABT4 Bit 3 0 0 AST3 ABT3 Bit 2 1 0 AST2 ABT2 Bit 1 1 0 AST1 ABT1 Bit 0 0 0 AST0 ABT0 AST: A-word Search Time. The value of these bits sets the A-word search time for all asynchronous Aword searches in units of 80ms (e.g. value of 1 is 80ms. value of 2 is 160ms, etc.) If the value is 0, the S5T8701 defaults to the 1-minute (MOT=1) or 4-minute (MOT=0) A-word search time controlled by the MOT bit in the configuration packet. (Value after reset=0) Asynchronous Battery-save Time. The value of these bits sets the battery save time (time from the beginning of one automatic noise detect to the beginning of the next automatic noise detect) in asynchronous mode in units of 80ms (e.g. value of 1 is 80ms, value of 2 is 160ms, etc.) If the value is 0, the battery save time is set to the default value of 1.5 seconds. The minimum allowed ABT is 320ms, therefore values of 1, 2, 3, and 4 are invalid. (Value after reset=0) ABT: 25 FLEX TM ROAMING DECODER II S5T8701 RECEIVER LINE CONTROL PACKET This packet gives the host control over the settings on the receiver control lines (S0-S7) in all modes except reset. In reset, the receiver control lines are in high impedance settings. The ID for the Receiver Line Control Packet is 15 (decimal). Table 10: Receiver Line Control Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 FRS7 CLS7 Bit 6 0 0 FRS6 CLS6 Bit 5 0 0 FRS5 CLS5 Bit4 0 0 FRS4 CLS4 Bit 3 1 0 FRS3 CLS3 Bit 2 1 0 FRS2 CLS2 Bit 1 1 0 FRS1 CLS1 Bit 0 1 0 FRS0 CLS0 FRS: Force Receiver Setting. Setting a bit to one will cause the corresponding CLS bit in this packet to override the internal receiver control settings on the corresponding receiver control line (S0 - S7). Clearing a bit gives control of the corresponding receiver control lines (S0 - S7) back to the S5T8701. (value after reset=0) Control Line Setting. If the corresponding FRS bit was set in this packet, these bits define what setting should be applied to the corresponding receiver control lines.(value after reset=0) CLS: 26 S5T8701 FLEX TM ROAMING DECODER II RECEIVER CONTROL CONFIGURATION PACKETS These packets allow the host to configure what setting is applied to the receiver control lines SO-S7, how long to apply the setting, and when to read the value of the LOBAT input pin. For a more detailed description of how the S5T8701 uses these settings see "Receiver Control" on page 55. The S5T8701 defines 12 different receiver control settings. Proper operation is not guaranteed if these settings are changed when decoding is enabled (i.e. the ON bit in the Control Packet is set). The IDs for these packets range from 16 to 27 (decimal). Receiver Off setting Packet Table 11: Receiver Off setting Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 CLS7 ST7 Bit 6 0 0 CLS6 ST6 Bit 5 0 0 CLS5 ST5 Bit4 1 0 CLS4 ST4 Bit 3 0 LBC CLS3 ST3 Bit 2 0 0 CLS2 ST2 Bit 1 0 0 CLS1 ST1 Bit 0 0 0 CLS0 ST0 LBC: Low Battery Check. If this bit is set, the S5T8701 will check the status of the LOBAT port just before leaving this receiver state. (value after reset=0) Control Line Setting. This is the value to be output on the receiver control lines (S0 - S7) for this receiver state. (value after reset=0) Step Time. This is the time the S5T8701 is to keep the receiver off before applying the first warm up state's receiver control value to the receiver control lines. The setting is in steps of 625us. Valid values are 625us (ST=01) to 159.375ms (ST=FF in hexadecimal). (value after reset=625us) CLS: ST: 27 FLEX TM ROAMING DECODER II S5T8701 RECEIVER WARM UP SETTING PACKETS Table 12: Receiver Warm Up Setting Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 s: 0 SE CLS7 0 Bit 6 0 0 CLS6 ST6 Bit 5 0 0 CLS5 ST5 Bit4 1 0 CLS4 ST4 Bit 3 0 LBC CLS3 ST3 Bit 2 s2 0 CLS2 ST2 Bit 1 s1 0 CLS1 ST1 Bit 0 s0 0 CLS0 ST0 Setting Number. Receiver control setting for which this packet's values are to be applied. The following truth table shows the names of each of the values for s that apply to this packet. s2 s1 s0 001 010 011 100 101 Setting Name Warm Up 1 Warm Up 2 Warm Up 3 Warm Up 4 Warm Up 5 SE: Step Enable. The receiver setting is enabled when the bit is set. If a step in the warm up sequence is disabled, the disabled step and all remaining steps will be skipped. (value after reset=0) Low Battery Check. If this bit is set, the S5T8701 will check the status of the LOBAT port just before leaving this receiver state. (value after reset=0) Control Line Setting. This is the value to be output on the receiver control lines (S0 - S7) for this receiver state. (value after reset=0) Step Time. This is the time the S5T8701 is to wait before applying the next state's receiver control value to the receiver control lines. The setting is in steps of 625us. Valid values are 625us (ST=01) to 79.375ms (ST=7F in hexadecimal), (value after reset=625us) LBC: CLS: ST: 28 S5T8701 FLEX TM ROAMING DECODER II 3200SPS SYNC SETTING PACKETS Table 13: 3200sps Sync Setting Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 CLS7 0 Bit 6 0 0 CLS6 ST6 Bit 5 0 0 CLS5 ST5 Bit4 1 0 CLS4 ST4 Bit 3 0 LBC CLS3 ST3 Bit 2 1 0 CLS2 ST2 Bit 1 1 0 CLS1 ST1 Bit 0 0 0 CLS0 ST0 LBC: Low Battery Check. If this bit is set, the S5T8701 will check the status of the LOBAT port just before leaving this receiver state. (value after reset=0) Control Line Setting. This is the value to be output on the receiver control lines (SO - S7) for this receiver state. (value after reset=0) Step Time. This is the time the S5T8701 is to wait before expecting good signals on the EXTS1 and EXTS0 signals after warming up. The setting is in steps of 625us. Valid values are 625us (ST=01) to 79.375ms (ST=7F in hexadecimal). (value after reset=625us) CLS: ST: 29 FLEX TM ROAMING DECODER II S5T8701 RECEIVER ON SETTING PACKETS Table 14: Receiver On Setting Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 CLS7 0 Bit 6 0 0 CLS6 0 Bit 5 0 0 CLS5 0 Bit4 1 0 CLS4 0 Bit 3 s3 LBC CLS3 0 Bit 2 s2 0 CLS2 0 Bit 1 s1 0 CLS1 0 Bit 0 S0 0 CLS0 0 s: Setting Number. Receiver control setting for which this packet's values are to be applied. The following truth table shows the names of each of the values for s that apply to this packet. s3 s2 s1 s0 0111 1000 1001 Setting Name 1600sps Sync 3200sps Data 1600sps Data LBC: Low Battery Check. If this bit is set, the S5T8701 will check the status of the LOBAT port just before leaving this receiver state. (value after reset=0) Control Line Setting. This is the value to be output on the receiver control lines (S0 - S7) for this receiver state. (value after reset=0) CLS: 30 S5T8701 FLEX TM ROAMING DECODER II RECEIVER SHUT DOWN SETTING PACKETS Table 15: Receiver Shut Down Setting Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 SE CLS7 0 Bit 6 0 0 CLS6 0 Bit 5 0 0 CLS5 ST5 Bit4 1 0 CLS4 ST4 Bit 3 1 LBC CLS3 ST3 Bit 2 0 0 CLS2 ST2 Bit 1 1 0 CLS1 ST1 Bit 0 s 0 CLS0 ST0 s: Setting Number. Receiver control setting for which this packet's values are to be applied. The following truth table shows the names of each of the values for s that apply to this packet. s 0 1 Setting Name Shut Down 1 Shut Down 2 SE: Step Enable. The receiver setting is enabled when the bit is set. If a step in the shut down sequence is disabled, all steps following the disabled step will be ignored. (value after reset=0) Low Battery Check. If this bit is set, the S5T8701 will check the status of the LOBAT port just before leaving this receiver state. (value after reset=0) Control Line Setting. This is the value to be output on the receiver control lines (S0 - S7) for this receiver state. (value after reset=0) Step Time. This is the time the S5T8701 is to wait before applying the next state's receiver control value to the receiver control lines. The setting is in steps of 625us. Valid values are 625us (ST=01) to 39.375ms (ST=3F in hexadecimal).(value after reset=625us) LBC: CLS: ST: 31 FLEX TM ROAMING DECODER II S5T8701 FRAME ASSIGNMENT PACKETS The FLEX protocol defines that each address of a FLEX pager is assigned a home frame and a battery cycle. The S5T8701 must be configured so that a frame that is assigned by one or more of the addresses' home frames and battery cycles has its corresponding configuration bit set. For example, if the S5T8701 has one enabled address and it is assigned to frame 3 with a battery cycle of 4, the AF bits for frames 3, 19, 35, 51, 67, 83, 99, and 115 should be set and the AF bits for all other frames should be cleared. When the S5T8701 is configured for manual collapse mode by setting the MCM bit in the Roaming Control Packet, the S5T8701 will not apply the received system collapse to the AF bits. The host should set the AF bits for all frames that should be decoded on all channels. For example, if frames 0 and 64 should be decoded on one channel and frames 4, 36, 68, and 100 should be decoded on another channel, all six of the corresponding AF bits should be set. The host can then change the receiver's carrier frequency after the S5T8701 decodes frames 0, 36, 64, and 100. There are 8 Frame Assignment Packets. The Packet IDs for these packets range from 32 to 39 (decimal). Table 16: Frame Assignment Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 AF15 AF7 Bit 6 0 0 AF14 AF6 Bit 5 1 0 AF13 AF5 Bit4 0 0 AF12 AF4 Bit 3 0 0 AF11 AF3 Bit 2 f2 0 AF10 AF2 Bit 1 f1 0 AF9 AF1 Bit 0 f0 0 AF8 AF0 f: Frame range. This value determines which 16 frames correspond to the 16 AF bits in the packet according to the following table. At least one of these bits must be set when the S5T8701 is turned on by setting the ON bit in the control packet. (value after reset=0) f2 f1 f0 000 001 010 011 100 1 01 110 111 AF15 Frame 127 Frame 111 Frame 95 Frame 79 Frame 63 Frame 47 Frame 31 Frame 15 AF0 Frame 112 Frame 96 Frame 80 Frame 64 Frame 48 Frame 32 Frame 16 Frame 0 AF: Assigned Frame. If a bit is set, the S5T8701 will consider the corresponding frame to be assigned via address's home frame and pager collapse. (value after reset=0) 32 S5T8701 FLEX TM ROAMING DECODER II USER ADDRESS ENABLE PACKET The User Address Enable Packet is used to enable and disable the 16 user address words. Although the host is allowed to change the user address words while the S5T8701 is decoding FLEX signals, the host must disable a user address word before changing it. The ID of the User Address Enable Packet is 120 (decimal). Table 17: User Address Enable Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 0 UAE15 UAE7 Bit 6 1 0 UAE14 UAE6 Bit 5 1 0 UAE13 UAE5 Bit4 1 0 UAE12 UAE4 Bit 3 1 0 UAE11 UAE3 Bit 2 0 0 UAE10 UAE2 Bit 1 0 0 UAE9 UAE1 Bit 0 0 0 UAE8 UAE0 UAE: User Address Enable. When a bit is set, the corresponding user address word is enabled. When it is cleared, the corresponding user address word is disabled. UAE0 corresponds to the user address word configured using a packet ID of 128, and UAE15 corresponds to the user address word configured using a packet ID of 143. (value after reset=0) 33 FLEX TM ROAMING DECODER II S5T8701 USER ADDRESS ASSIGNMENT PACKETS The S5T8701 has 16 user address words. Each word can be programmed to be a short address, part of a long address, or the first part of a network ID. The addresses are configured using the Address Assignment Packets. Each user address can be configured as long or short and tone-only or regular (network ID's are short and regular). Although the host is allowed to send these packets while the S5T8701 is on, the host must disable the user address word by clearing the corresponding UAE bit in the User Address Enable Packet before changing any of the bits in the corresponding User Address Assignment Packet. This method allows for easy reprogramming of user addresses without disrupting normal operation. The IDs for these packets range from 128 to 143 (decimal). Table 18: User Address Assignment Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 1 0 A15 A7 Bit 6 0 LA A14 A6 Bit 5 0 TOA A13 A5 Bit4 0 A20 A12 A4 Bit 3 a3 A19 A11 A3 Bit 2 a2 A18 A10 A2 Bit 1 a1 A17 A9 A1 Bit 0 a0 A16 A8 A0 a: User Address Word Number. This specifies which address word is being configured. A zero in this field corresponds to address index zero (AI=0) in the Address Packet received from the S5T8701 when an address is detected. See "Address Packet" on page 41 for a description of the address index field. Long address. When this bit is set, the address is considered a long address. Both words of a long address must have this bit set. The first word of a long address must have an even address index and the second word must be in the address index immediately following the first word. Tone-Only Address. When this bit is set, the S5T8701 will consider this address a tone-only address and will not decode a vector word when the address is received. If the TOA bit of a long address word is set, the TOA bit of the other word of the long address must also be set. Address word. This is the 21 bit value of the address word. Valid FLEX messaging addresses or Network ID's may be used. LA: TOA: A: 34 S5T8701 FLEX TM ROAMING DECODER II DECODER-TO-HOST PACKET DESCRIPTIONS The following sections describe the packets of information that will be sent from the S5T8701 to the host. In all cases the packets are sent MSB first (bit 7 of byte 3 = bit 31 of the packet = MSB). The S5T8701 decides what data should be sent to the host. If the S5T8701 is disabled through the checksum feature (see "Checksum Packet" on page 16 for a description of the checksum feature) the Part ID Packet will be sent. Data Packets relating to data received over the air are buffered in the 32 packet transmit buffer. The Data packets include Block Information Word Packets, Address Packets, Vector Packets, and Message Packets. If the S5T8701 is enabled and a receiver shutdown packet is pending, the receiver shutdown packet will be sent. If there is no receiver shutdown packet pending, but there is a roaming status packet pending, the roaming status packet will be sent. If neither the receiver shutdown packet nor the roaming status packet is pending and there is data in the transmit buffer, a packet from the transmit buffer will be sent. Otherwise, the S5T8701 will send the Status Packet (which is not buffered). In the event of a buffer overflow, the S5T8701 will automatically stop decoding and clear the buffer. It is recommended that the Host be designed to empty the FIFO buffer every block with enough time left over to read a status packet. This would ensure that any applicable Status Packet would be received within 1 block of the new status being available. Part ID register 32 Receiver shutdown register 32 Roaming status register 32 M U X 32 32 32x32 data packet FIFO transmit buffer Status register 32 SPI transmit register MISO Figure 10: FLEX decoder IC SPI Transmit Functional Block Diagram 35 FLEX TM ROAMING DECODER II S5T8701 BLOCK INFORMATION WORD PACKET The Block Information Field is the first field following the synchronization codes of the FLEX protocol. This field contains information about the frame such as number of addresses and messages, information about current time, the channel ID, channel attributes, etc. The first block information word of each phase is used internally to the S5T8701 and is never transmitted to the host with the exception of the system collapse which is sent to the host when the S5T8701 is in manual collapse mode. Time block information words 2-4 can be optionally sent to the host by setting the SBI bit in the control packet (see "Control Packet" on page 21). All block information words 2-4 can be optionally sent to the host by setting the ABI bit in the roaming control packet. When the SBI or ABI bit is set and any block information word 2-4 is received with an uncorrectable number of bit errors, the S5T8701 will send the block information word to the host with the e bit set regardless of the value of the f field in the block information word. The S5T8701 does not support decoding of the vector and message words associated with the Data/System Message block info word (f=101). The ID of a Block Information Word Packet is 0 (decimal). Table 19: Block Information Word Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 e x s7 Bit 6 0 p1 x s6 Bit 5 0 p0 s13 s5 Bit4 0 x s12 s4 Bit 3 0 x s11 s3 Bit 2 0 f2 s10 s2 Bit 1 0 f1 s9 s1 Bit 0 0 f0 s8 s0 e: Set if more than 2 bit errors are detected in the word or if the check character calculation fails after error correction has been performed. Phase on which the block information word was found (0=a, 1=b, 2=c, 3=d) Unused bits. The value of these bits is not guaranteed. Word Format Type. The value of these bits modify the meaning of the s bits in this packet as described in the BIW word descriptions in the s bit definition below. p: x: f: 36 S5T8701 FLEX TM ROAMING DECODER II s: These are the information bits of the block information word. The definition of these bits depend on the f bits in this packet. The following table describes the block information words. f2f1f0 000 001 010 011 100 101 110 111 a b b a a b a a s13 i8 m3 S2 s12 i7 m2 S1 s11 i6 m1 S0 s10 i5 m0 M5 s9 i4 d4 M4 s8 i3 d3 M3 s7 i2 d2 M2 s6 i1 d1 M1 s5 i0 d0 M0 s4 C4 Y4 H4 s3 C3 Y3 H3 s2 C2 Y2 H2 s1 C1 Y1 H1 s0 C0 Y0 H0 Description Local ID, Coverage Zone Month ,Day, Year Second ,Minute, Hour Reserved by FLEX protocol for future use Reserved by FLEX protocol for future use z9 z8 z7 z6 z5 z4 z3 z2 z1 z0 A3 A2 A1 A0 System Message Country Code, Traffic Management Flags Reserved by FLEX protocol for future use c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 T3 T2 T1 T0 a. b. Will be decoded only if the ABI bit is set Will be decoded only if the SBI or ABI bit is set 37 FLEX TM ROAMING DECODER II S5T8701 ADDRESS PACKET The Address Field follows the Block Information Field in the FLEX protocol. It contains all of the address in the frame. If less than three bit errors are detected in a received address word and it matches an enabled address assigned to the S5T8701, an Address Packet will be sent to the host processor. The Address Packet contains assorted data about the address and its associated vector and message. The ID of an Address Packet is 1 (decimal). Table 20: Address Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 PA AI7 TOA Bit 6 0 p1 AI6 WN6 Bit 5 0 p0 AI5 WN5 Bit4 0 LA AI4 WN4 Bit 3 0 x AI3 WN3 Bit 2 0 x AI2 WN2 Bit 1 0 x AI1 WN1 Bit 0 1 x AI0 WN0 PA: p: LA: AI: Priority Address. Set if the address was received as a priority address. Phase on which the address was detected (0=a, 1=b, 2=c, 3=d) Long Address type. Set if the address was programmed in the S5T8701 as a long address. Address Index (valid values are 0 through 15 and 128 through 159). The index identifies which of the addresses was detected. Values 0 through 15 correspond to the 16 programmable address words. Values 128 through 143 correspond to the 16 temporary addresses. Values 144 through 159 correspsond to the 16 operator messaging addresses. For long addresses, the address detect packet will only be sent once and the index will refer to the second word of the address. Tone Only Address. Set if the address was programmed in the S5T8701 as a tone-only address. This bit will never be set for temporary or operator messaging addresses. No vector word will be sent for tone-only addresses. Word number of vector (2 - 87). Describes the location in the frame of the vector word for the detected address. This value is invalid for this packet if the TOA bit is set. Unused bits. The value of these bits is not guaranteed. TOA: WN: x: 38 S5T8701 FLEX TM ROAMING DECODER II VECTOR PACKET The Vector Field follows the Address Field in the FLEX protocol. Each Vector Packet must be matched to its corresponding Address Packet. The ID of the vector packet is the word number where the vector word was received in the frame. This value corresponds to the WN bits sent in the associated address packet. The phase information in both the Address Packet and the Vector Packet must also match. It is important to note for long addresses, the first message word will be transmitted in the word location immediately following the associated vector. See "Message Building" on page 59 for a message building example. In this case, the word number (identified by b6 to b0) in the Vector Packet will indicate the message start of the second message word if the message is longer than 1 word. There are several types of vectors - 3 types of Numeric Vectors, a Short Message / Tone Only Vector, a Hex / Binary Vector, an Alphanumeric Vector, a Secure Message Vector, and a Short Instruction Vector. Each is described in the following pages. One of the modes of the Short Instruction Vector is used for assigning temporary addresses that may be associated with a group call. The Numeric, Hex / Binary, Alphanumeric, and Secure Message Vector Packets have associated Message Word Packets in the message field. The host must use the n and b bits of the vector word to calculate what message word locations are associated with the vector. Both the message word locations and the phase must match. Four of the vectors (Hex / Binary, Alphanumeric, Secure Message, and Short Instruction) enable the S5T8701 to begin the all frame mode. This mode is required to allow for the decoding of temporary addresses and / or fragmented messages. The host disables the All Frame Mode after the proper time by writing to the decoder via the All Frame Mode Packet. See "Building a Fragmented Message" on page 61 and "Operation of a Temporary Address" on page 64 for more information. For any Address Packet sent to the host (except tone-only addresses), a corresponding Vector Packet will always be sent. If more than two bit errors are detected (via BCH calculations, parity calculations, check character calculations, or value validation) in the vector word the e bit will be set and the message words will not be sent. 39 FLEX TM ROAMING DECODER II S5T8701 NUMERIC VECTOR PACKET Table 21: Numeric Vector Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 e x n0 Bit 6 WN6 p1 x b6 Bit 5 WN5 p0 K3 b5 Bit4 WN4 x K2 b4 Bit 3 WN3 x K1 b3 Bit 2 WN2 V2 K0 b2 Bit 1 WN1 V1 n2 b1 Bit 0 WN0 V0 n1 b0 V: V2 V1 V0 011 100 111 Vector type identifier. Name Standard Numeric Vector Special Format Numeric Vector Numbered Numeric Vector Description No special formatting of characters is specified Formatting of the received characters is predetermined by special rules in the host. The received information has been numbered by the service provider to indicate all messages have been properly received WN: e: Word number of vector (2 - 87 decimal). Describes the location of the vector word in the frame. Set if more than 2 bit errors are detected in the word, if the check character calculation fails after error correction has been performed, or if the vector value is determined to be invalid. Phase on which the vector was found (0=a, 1=b,2=c, 3=d) Beginning check bits of the message. Number of message words in the message including the second vector word for long addresses (000=1 word message, 001=2 word message, etc.). For long addresses, the first message word is located in the word location that immediately follows the associated vector. Word number of message start in the message field (3 - 87 decimal). For long addresses, the word number indicates the location of the second message word. Unused bits. The value of these bits is not guaranteed. p: K: n: b: x: 40 S5T8701 FLEX TM ROAMING DECODER II SHORT MESSAGE / TONE ONLY VECTOR Table 22: Short Message / Tone Only Vector Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 V: WN: e: 0 e x d5 Bit 6 WN6 p1 x d4 Bit 5 WN5 p0 d11 d3 Bit4 WN4 x d10 d2 Bit 3 WN3 x d9 d1 Bit 2 WN2 V2 d8 d0 Bit 1 WN1 V1 d7 t1 Bit 0 WN0 V0 d6 t0 010 for a Short Message / Tone Only Vector Word number of vector (2 - 87 decimal). Describes the location of the vector word in the frame. Set if more than 2 bit errors are detected in the word or, if after error correction, the check character calculation fails. Phase on which the vector was found (0=a, 1=b, 2=c, 3=d) Data bits whose definition depend on the value of t in this packet according to the following table. Note that if this vector is received on a long address and the e bit in this packet is not set, the decoder will send a Message Packet from the word location immediately following the Vector Packet. Except for the short message on a non-network address (t=0), all message bits in the Message Packet are unused and should be ignored. p: d: t 1t 0 00 00 01 10 d1 1 d1 0 d9 c1 T1 s6 d8 c0 d7 b3 d6 b2 d5 b1 d4 b0 d3 a3 d2 a2 d1 a1 d0 Description c3 T3 s8 s1 c2 T2 s7 s0 a0 Short Numeric: 3 numeric charsa when on a messaging address T0 M2 M1 M0 A4 A3 A2 A1 A0 Part of NID when on a Network Address s5 s4 s3 s2 s1 s0 S2 S1 S0 Tone Only: 8 source (S) and 9 unused bits(s) R0 N5 N4 N3 N2 N1 N0 S2 S1 S0 Tone only: 8 source (s),message number(N),message retrieval flag (R), and 2 unused bits(s) spare message type For long addresses, an extra 5 characters are sent in the Message Packet immediately following the Vector Packet. 11 a. t: x: Message type. These bits define the meaning of the d bits in this packet. Unused bits. The value of these bits is not guaranteed. 41 FLEX TM ROAMING DECODER II S5T8701 HEX / BINARY, ALPHANUMERIC, AND SECURE MESSAGE VECTOR Table 23: HEX / Binary, Alphanumeric, and Secure Message Vector Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 e x n0 Bit 6 WN6 p1 x b6 Bit 5 WN5 p0 n6 b5 Bit4 WN4 x n5 b4 Bit 3 WN3 x n4 b3 Bit 2 WN2 V2 n3 b2 Bit 1 WN1 V1 n2 b1 Bit 0 WN0 V0 n1 b0 V: Vector type identifier. V2 V1 V0 000 101 110 Type Secure Alphanumeric Hex / Binary WN: e: Word number of vector (2 - 87 decimal). Describes the location of the vector word in the frame. Set if more than 2 bit errors are detected in the word, if the check character calculation fails after error correction has been performed, or if the vector value is determined to be invalid. Phase on which the vector was found (0=a, 1=b, 2=c, 3=d) Number of message words in this frame including the first Message word that immediately follows a long address vector. Valid values are 1 through 85 decimal Word number of message start in the message field. Valid values are 3 through 87 decimal. Unused bits. The value of these bits is not guaranteed. p: n: b: x: NOTE: For long addresses, the first Message Packet is sent from the word location immediately following the word location of the Vector Packet. The b bits indicate the second message word in the message field if one exists. 42 S5T8701 FLEX TM ROAMING DECODER II SHORT INSTRUCTION VECTOR Table 24: Short Instruction Vector Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 e x d4 Bit 6 WN6 p1 x d3 Bit 5 WN5 p0 d10 d2 Bit4 WN4 x d9 d1 Bit 3 WN3 x d8 d0 Bit 2 WN2 V2 d7 i2 Bit 1 WN1 V1 d6 i1 Bit 0 WN0 V0 d5 i0 V: WN: e: 001 for a Short Instruction Vector. Word number of vector (2 - 87 decimal). Describes the location of the vector word in the frame. Set if more than 2 bit errors are detected in the word or, if after error correction the check character calculation fails. Phase on which the vector was found (0=a, 1=b, 2=c, 3=d) Data bits whose definition depend on the i bits in this packet according to the following table. Note that if this vector is received on a long address and the e bit in this packet is not set, the decoder will send a Message Packet immediately following the Vector Packet. All message bits in the message packet are unused and should be ignored for all modes except the Temporary address assignment with MSN (i2i1i0=010). d10 a3 d10 a3 d9 a2 d9 a2 d8 a1 d8 a1 d7 a0 d7 a0 d6 f6 d6 f6 d5 f5 d5 N5 d4 f4 d4 N4 d3 f3 d3 N3 d2 f2 d2 N2 d1 f1 d1 N1 d0 f0 d0 N0 Description Temporary address assignmenta 11 Event Flags for System Event Temporary address assignment with MSNb Reserved Reserved Reserved Reserved Reserved for test Assigned temporary address (a) and assigned frame (f). See "Operation of a Temporary Address" on page 64 for a description of the use of these fields Assigned temporary address (a), MSb of assigned frame (f6), and message sequence number (N). The message packet sent with this instruction on long addresses contains extra frame information, see "Operation of a Temporary Address" on page 64 for a description and for details on the use of the other fields. Instruction type. These bits define the meaning of the d bits in this packet. Unused bits. The value of these bits is not guaranteed. p: d: i2 i1 i0 000 001 010 011 100 101 110 111 a. b. i: x: 43 FLEX TM ROAMING DECODER II S5T8701 MESSAGE PACKET The Message Field follows the Vector Field in the FLEX protocol. It contains the message data, checksum information, and may contain fragment numbers and message numbers. If the error bit of a vector word is not set and the vector word indicates that there are message words associated with the page, the message words are sent in Message Packets. The ID of the Message Packet is the word number where the message word was received in the frame. Table 25: Message Packet Bit Assignments Bit 7 Byte 5 Byte 2 Byte 1 Byte 0 0 e i15 i7 Bit 6 WN6 p1 i14 i6 Bit 5 WN5 p0 i13 i5 Bit4 WN4 i20 i12 i4 Bit 3 WN3 i19 i11 i3 Bit 2 WN2 i18 i10 i2 Bit 1 WN1 i17 i9 i1 Bit 0 WN0 i16 i8 i0 WN: Word number of message word (3 - 87 decimal). Describes the location of the message word in the frame. Set if more than 2 bit errors are detected in the word. Phase on which the message word was found (0=a, 1=b, 2=c, 3=d) These are the information bits of the message word. The definitions of these bits depend on the vector type and which word of the message is being received. e: p: i: 44 S5T8701 FLEX TM ROAMING DECODER II ROAMING STATUS PACKET The S5T8701 will prompt the host to read a Roaming Status Packet if RSR, MS1, MFI, MS2, MBI, MAW, NBU NDR1, NDR0, or SCU is set. Table 26: Roaming Status Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 RSR x x Bit 6 1 MS1 x x Bit 5 1 MFI x x Bit4 0 MS2 x x Bit 3 0 MBI x SCU Bit 2 0 MAW x RSC2 Bit 1 0 NBU NDR1 RSC1 Bit 0 0 n NDR0 RSC0 RSR: Re-synchronization Signal Received. Set when the S5T8701 detected a re-synchronization signal and the host configured the S5T8701 to ignore it via the IRS bit in the roaming control packet. This bit is cleared when read. Missed Synchronization 1. Set when the S5T8701 failed to detect the first synchronization pattern (A / A) of a FLEX frame and the S5T8701 was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is cleared when read. Missed Frame Information word. Set when the frame information word is received with an uncorrectable number of errors and the S5T8701 was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is cleared when read. Missed Synchronization 2. Set when the S5T8701 failed to detect the second synchronization pattern (C / C) of a frame and the S5T8701 was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is cleared when read. Missed Block Information word 1. Set when at least one of the block information word ones is received with an uncorrectable number of errors and the S5T8701 was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is set no more than once per frame regardless of the number of missed block information word 1's in the frame. This bit is cleared when read. Missed Address Word. Set when any address words in the address field is received with an uncorrectable number of errors and the S5T8701 was configured to report missed frame information via the MFC bit in the roaming control packet. This bit is set no more than once per frame regardless of the number of missed address words in the frame. This bit is cleared when read. Network Bit Update. Set when the NBC bit in the roaming control packet is set and a frame information word is received with a correctable number of errors. This bit will not be set when the frame information word is not received due to missing the first synchronization pattern (A / A). This bit is cleared when read. Network bit value. When NBU is set, this is the value of the n bit in the last received frame information word. MS1: MFI: MS2: MBI: MAW: NBU: n: 45 FLEX TM ROAMING DECODER II S5T8701 NDR: Noise Detect Result. These bits indicate the result of a noise detect. The results of noise detects initiated by setting the SND bit in the roaming control packet will always be reported. The results of the automatic noise detects performed in asynchronous mode will only be reported if the RND bit is set in the roaming control packet. When continuous noise detects during block data are enabled by setting the CND bit in the roaming control packet, only the "No FLEX signal detected" result will be reported. These bits are cleared when read. NDR 00 01 10 11 Noise Detect Result No Information Noise Detect was abandoned FLEX signal detected FLEX signal not detected SCU: System Collapse Update. Set when the S5T8701 is configured for manual collapse mode by setting the MCM bit in the roaming control packet and the system collapse of a frame is received. This bit is set no more than once per frame regardless of the number of phases in the frame. This bit will not be set in frames in which no block information word ones is received properly. This bit is cleared when read. Received System Collapse. When SCU is set, this value represents the system collapse value that was received in the frame RSC: 46 S5T8701 FLEX TM ROAMING DECODER II RECEIVER SHUTDOWN PACKET The Shutdown Packet is sent in both synchronous and asynchronous mode. It is designed to indicate to the host that the receiver is turned off and how much time there is until the S5T8701 will automatically turn it back on. Table 27: Receiver Shut Down Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 FNV TNF7 FCO Bit 6 1 CF6 TNF6 NAF6 Bit 5 1 CF5 TNF5 NAF5 Bit4 1 CF4 TNF4 NAF4 Bit 3 1 CF3 TNF3 NAF3 Bit 2 1 CF2 TNF2 NAF2 Bit 1 1 CF1 TNF1 NAF1 Bit 0 0 CF0 TNF0 NAF0 FNV: Frame Number Valid. This bit is set if the last decoded frame info word was correctable and the frame number was the expected value. When in asynchronous mode, this value will be 0. Current Frame. When in synchronous mode, this is the current frame number. This value is latched on the negative edge of the READY line when this packet is sent to the host. The value of this field is valid only if the S5T8701 is in synchronous mode and the FIV bit in the status packet is set. When in asynchronous mode, this value will be 0. Time to Next Frame. When in synchronous mode TNF indicates the time to the start of the A-word check if the S5T8701 were to warm up for the next frame. When in asynchronous mode TNF indicates the time to the start of the next automatic noise detect. See "Using the Receiver Shutdown Packet" on page 66 for an explanation on how to use this value. This value is latched on the negative edge of the READY line when this packet is sent to the host. Frame Carried On. Set if the S5T8701 is decoding the next frame due to the reception of a nonzero carry-on value in a previous frame. When in synchronous mode, this value will be 0. Next Assigned Frame. This is the frame number of the next frame the S5T8701 was scheduled to decode when the receiver shut down. The value of this field is valid only if the S5T8701 is in synchronous mode and the FIV bit in the status packet is set. When in asynchronous mode this value will be 0. CF: TNF: FCO: NAF: 47 FLEX TM ROAMING DECODER II S5T8701 STATUS PACKET The Status Packet contains various types of information that the host may require. The Status Packet will be sent to the host whenever the S5T8701 is polled and has no other data to send. The S5T8701 can also prompt the host to read the Status Packet due to events for which the S5T8701 was configured to send it (see "Configuration Packet" on page 18 and "Control Packet" on page 21 for a detailed description of the bits). The S5T8701 will prompt the host to read a Status Packet if the... 1. SMU bit in the Status Packet and the SME bit in the Configuration Packet are set. 2. MT bit in the Status Packet and the MTE bit in the Configuration Packet are set. 3. EOF bit in the Status Packet is set. 4. LBU bit in the Status Packet is set. 5. EA bit in the Status Packet is set. 6. BOE bit in the Status Packet is set. The ID of the Status Packet is 127 (decimal). Table 28: Status Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 0 FIV SM SMU Bit 6 1 f6 LB LBU Bit 5 1 f5 x x Bit4 1 f4 x MT Bit 3 1 f3 c3 x Bit 2 1 f2 c2 EOF Bit 1 1 f1 c1 EA Bit 0 1 f0 C0 BOE FIV: Frame Info Valid. Set when a valid frame info word has been received since becoming synchronous to the system and the f and c fields contain valid values. If this bit is clear, no valid frame info words have been received since the S5T8701 became synchronous to the system. This value will change from 0 to 1 at the end of block 0 of the frame in which the 1st frame info word was properly received. It will be cleared when the S5T8701 goes into asynchronous mode. This bit is initialized to 0 when the S5T8701 is reset and when the S5T8701 is turned off by clearing the ON bit in the Control Packet. Current frame number. This value is updated every frame regardless of whether the S5T8701 needs to decode the frame. This value will change to its proper value for a frame at the end of block 0 of the frame. The value of these bits is not guaranteed when FIV is 0. Synchronous Mode. This bit is set when the S5T8701 is synchronous to the system. The S5T8701 will set this bit when the first synchronization words are received. It will clear this bit when the S5T8701 has not received both synchronization words in any frame for 8, 16, or 32 minutes (depending on the number of assigned frames and the system collapse). This bit is initialized to 0 when the S5T8701 is reset and when it is turned off by clearing the ON bit in the Control Packet Low Battery. Set to the value last read from the LOBAT pin. The host controls when the LOBAT pin is read via the Receiver Control Packets. This bit is initialized to 0 at reset. It is also initialized to the inverse of the LBP bit in the Configuration Packet when the S5T8701 is turned on by setting the ON bit in the Control Packet. f: SM: LB: 48 S5T8701 FLEX TM ROAMING DECODER II c: Current system cycle number. This value is updated every frame regardless of whether the S5T8701 needs to decode the frame. This value will change to its proper value for a frame at the end of block 0 of the frame. The value of these bits is not guaranteed when FIV is 0. Synchronous Mode Update. Set if the SM bit has been updated in this packet. When the S5T8701 is turned on, this bit will be set when the first synchronization words are found (SM changes to 1) or when the first synchronization search window after the S5T8701 is turned on expires (SM stays 0). The latter condition gives the host the option of assuming the paging device is in range when it is turned on, and displaying out-of-range only after the initial A search window expires. After the initial synchronous mode update, the SMU bit will be set whenever the S5T8701 transitions from/to synchronous mode. Cleared when read. Changes in the SM bit due to turning off the S5T8701 will not cause the SMU bit to be set. This bit is initialized to 0 when the S5T8701 is reset. Low Battery Update. Set if the value on two consecutive reads of the LOBAT pin yielded different results. Cleared when read. The host controls when the LOBAT pin is read via the Receiver Control Packets. Changes in the LB bit due to turning on the S5T8701 will not cause the LBU bit to be set. This bit is initialized to 0 when the S5T8701 is reset. Minute Time-out. Set if one minute has elapsed. Cleared when read. This bit is initialized to 0 when the S5T8701 is reset. End Of Frame. Set when the S5T8701 is in all frames mode and the end of frame has been reached. The S5T8701 is in all frames mode if the all frames mode enable counter is non-zero, if any temporary address enabled counter is non-zero, or if the FAF bit in the All Frame Mode Packet is set. Cleared when read. This bit is initialized to 0 when the S5T8701 is reset. End of Addresses. If EAE of the control packet is set and an address is detected in a frame, EA will be set after the S5T8701 processes the last address in the frame. Since data packets take priority over the status packet, the status packet with the EA bit set is guaranteed to come after all address packets for the frame. Cleared when read. This bit is initialized to 0 when the S5T8701 is reset. Buffer Overflow Error. Set when information has been lost due to slow host response time. When the data packet FIFO transmit buffer on the S5T8701 overflows, the S5T8701 clears the transmit buffer, turns off decoding by clearing the ON bit in the Control Packet, and sets this bit. Cleared when read. This bit is initialized to 0 when the S5T8701 is reset. Unused bits. The value of these bits is not guaranteed. SMU: LBU: MT: EOF: EA: BOE: x: 49 FLEX TM ROAMING DECODER II S5T8701 PART ID PACKET The Part ID Packet is sent by the S5T8701 whenever the S5T8701 is disabled due to the checksum feature. See "Checksum Packet" on page 16 for a description of the checksum feature. Since the S5T8701 is disabled after reset, this is the first packet that will be received by the host after reset. The ID of the Part ID Packet is 255 (decimal). Table 29: Part ID Packet Bit Assignments Bit 7 Byte 3 Byte 2 Byte 1 Byte 0 1 MDL1 CID7 REV7 Bit 6 1 MDL0 CID6 REV6 Bit 5 1 CID13 CID5 REV5 Bit4 1 CID12 CID4 REV4 Bit 3 1 CID11 CID3 REV3 Bit 2 1 CID10 CID2 REV2 Bit 1 1 CID9 CID1 REV1 Bit 0 1 CID8 CID0 REV0 MDL: CID: Model. This identifies the FLEX decoder model. Current value is 0. Compatibility ID. This value describes the FLEX decoder ICs to which this part is backwards compatible. See table below for meaning and current value. Indicates this IC can be used in place of FLEX Alphanumeric Decoder Ia FLEX Roaming Decoder I FLEX Numeric Decoder b Bit CID0 CID1 CID2 Value for FLEXTM Roaming Decoder II 1 (TRUE) 1 (TRUE) 0 (FALSE) a. b. Compatibility to FLEX Alphanumeric Decoder II is indicated by MDL set to 0, CID0 set to 1, and REV greater than or equal to 7. Compatibility to FLEX Roaming Decoder II is indicated by MDL set to 0, CID1 set to 1, and REV greater than or equal to 8. 50 S5T8701 FLEX TM ROAMING DECODER II REV: Revision. This identifies the revision and manufacturer of the FLEX decoder IC. The following table lists the currently available part ID's of the FLEX Decoder IC family. Revision FLEX Alphanumeric Decoder I FLEX Alphanumeric Decoder I FLEX Alphanumeric Decoder I FLEX Alphanumeric Decoder II FLEX Roaming Decoder I FLEX Roaming Decoder I FLEX Roaming Decoder II FLEX Roaming Decoder II FLEX Numeric Decoder Manufacturer Texas Instruments Motorola Semiconductor Products Sector Philips Motorola Semiconductor Products Sector Motorola Semiconductor Products Sector Texas Instruments Motorola Semiconductor Products Sector Samsung Electronics Texas Instruments Part ID Packet (Hex) 00 01 03 00 01 04 00 01 06 00 01 07 00 03 03 00 03 05 00 03 09 00 03 14 00 04 01 51 FLEX TM ROAMING DECODER II S5T8701 APPENDIX A : APPLICATION NOTES RECEIVER CONTROL Introduction The S5T8701 has 8 programmable receiver control lines (S0 - S7). The host has control of the receiver warm up and shut down timing as well as all of the various settings on the control lines through configuration registers on the S5T8701. The configuration registers for most settings allow the host to configure what setting is applied to the control lines. how long to apply the setting, and if the LOBAT input pin is polled before changing from the setting. With this programmability, the S5T8701 should be able to interface with many off-the-shelf receiver ICs. When using the internal demodulator (i.e. when the IDE bit of the configuration packet is set), the S0 pin becomes the input for the demodulator and the S0 register setting in the receiver control configuration packets controls the tracking mode of the peak and valley detectors for the internal data slicer. When the S0 bit is set in a receiver setting, the internal data slicer will be in fast track mode. When S0 bit is cleared in a receiver setting, the internal data slicer will be in slow track mode. For details on the configuration of the receiver control settings, see "Receiver Control Configuration Packets" on page 30. Receiver Settings at Reset The receiver control ports are three-state outputs which are set to the high-impedance state when the S5T8701 is reset and until the corresponding FRS bit in the Receiver Line Control Packet is set or until the S5T8701 is turned on by setting the ON bit in the Control Packet. This allows the designer to force the receiver control lines to the receiver off setting with external pull-up or pull-down resistors before the host can configure these settings in the S5T8701. When the S5T8701 is turned on, the receiver control ports are driven to the settings configured by the "Receiver Control Configuration Packets" on page 30 until the S5T8701 is reset again. Automatic Receiver Warm Up Sequence The S5T8701 allows for up to 6 steps associated with warming up the receiver. When the S5T8701 automatically turns on the receiver, it starts the warm up sequence 160ms before it requires valid signals at the EXTS0 and EXTS1 input pins. (or the equivalent internal signals when using the internal demodulator/data slicer). The first step of the warm up sequence involves leaving the receiver control lines in the "Off" state for the amount of time programmed for "Warm Up Off Time". At the end of the "Warm Up Off Time", the first warm up setting, if enabled, is applied to the receiver control lines for the amount of time programmed for that setting. Each subsequent warm up setting is applied to the receiver control lines for their corresponding time until a disabled warm up setting is found. At the end of the last used warm up setting, the "1600sps Sync Setting" or the "3200sps Sync Setting" is applied to the receiver control lines depending on the current state of the S5T8701. The sum total of all of the used warm up times and the "Warm Up Off Time" must not exceed 160ms. If it exceeds 160ms, the S5T8701 will execute the receiver shut down sequence at the end of the 160ms warm up period. The receiver warm up sequence while decoding when all warm up settings are enabled is shown in figure 11 on page 56. 52 S5T8701 FLEX TM ROAMING DECODER II 160 ms Warm up off time Warm up time 1 Warm up setting 1 Warm up time 2 Warm up setting 2 Warm up time 3 Warm up setting 3 Warm up time 4 Warm up setting 4 Warm up time 5 Warm up setting 5 1600sps or 3200sps sync setting Receiver control line setting Off Possible LOBAT check Possible LOBAT check Possible LOBAT check Possible LOBAT check Possible LOBAT check Possible EXTS1 & LOBAT EXTS0 signals check are expected to be valid here Figure 11: Automatic Receiver Warm Up Sequence HOST INITIATED RECEIVER WARM UP SEQUENCE The host can cause the S5T8701 to warm-up the receiver in three ways: (1) by turning on S5T8701 by setting the ON bit in the control packet; (2) by requesting a noise detect by setting the SND bit in the roaming control packet; or (3) by requesting an A-word search by setting the SAS bit in the roaming control packet. When the S5T8701 warms up the receiver in response to a host request, the first warm up setting, if enabled, is applied to the receiver control lines for the amount of time programmed for that setting. Each subsequent warm up setting is applied to the receiver control lines for their corresponding time until a disabled warm up setting is found. Once a disabled warm up setting is found, the "3200sps Sync Setting" (for ON and SND warm ups) or the "1600sps Sync Setting" (for SAS warm ups) is applied to the receiver control lines and the decoder does not expect valid signal until after the "3200sps Sync Warm Up Time" (for ON, SND, and SAS warm ups) has expired. In figure 12 on page 56 the receiver warm up sequence when the host initiates a warm-up sequence and when all warm up settings are enabled is shown. Warm up time 1 Warm up time 2 Warm up setting 2 Warm up time 3 Warm up setting 3 Warm up time 4 Warm up setting 4 Receiver control line setting Off Warm up setting 1 Warm up 3200sps time 5 sync warm up time Warm up 3200sps setting 5 sync setting Possible EXTS1 & LOBAT EXTS0 signals check are expected to be valid here Possible LOBAT check Possible LOBAT check Possible LOBAT check Possible LOBAT check Possible LOBAT check Figure 12: Host Initiated Receiver Warm Up Sequence 53 FLEX TM ROAMING DECODER II S5T8701 RECEIVER SHUT DOWN SEQUENCE The S5T8701 allows for up to 3 steps associated with shutting down the receiver. When the S5T8701 decides to turn off the receiver, the first shut down setting, if enabled, is applied to the receiver control lines for the corresponding shut down time. At the end of the last used shut down time, the "Off" setting is applied to the receiver control lines. If the first shut down setting is not enabled, the S5T8701 will transition directly from the current on setting to the "Off" setting. The receiver turn off sequence when all shut down settings are enabled is shown in figure 13 on page 57 If the receiver is on or being warmed up when the decoder is turned off (by clearing the ON bit in the Control Packet), the S5T8701 will execute the receiver shutdown sequence. If the S5T8701 is executing the shut down sequence when the S5T8701 is turned on (by setting the ON bit in the Control Packet), the S5T8701 will complete the shut down sequence before starting the warm up sequence. Shut down time 1 Shut down time 2 Shut down setting 2 Possible LOBAT check Off Receiver control line setting 1600sps or 3200sps sync or data setting Possible LOBAT check Shut down setting 1 Possible LOBAT check Figure 13: Receiver Shut Down Sequence 54 S5T8701 FLEX TM ROAMING DECODER II MISCELLANEOUS RECEIVER STATES In addition to the warm up and shut down states, the S5T8701 has four other receiver states. When these settings are applied to the receiver control lines, the S5T8701 will be decoding the EXTS1 and EXTS0 input signals. The timing of these signals and their duration depends on the data the S5T8701 decodes. The four settings are as follows: 1600sps Sync Setting: This setting is applied when the S5T8701 is searching for a 1600 symbols per second signal. 3200sps Sync Setting: This setting is applied when the S5T8701 is searching for a 3200 symbols per second signal. 1600sps Data Setting: This setting is applied after the S5T8701 has found the C or C sync word in a 1600 symbols per second frame. 3200sps Data Setting: This setting is applied after the S5T8701 has found the C or C sync word in a 3200 symbols per second frame. Some examples of how these settings will be used in the S5T8701 are shown In figure 14 on page 58. Flex signal Receiver control line setting example #1 Block 10 Sync 1 Frame info Sync 2 Block 0 1600sps data or 3200sps data or last used warm up setting Possible LOBAT check 1600sps sync setting 3200sps sync setting Possible LOBAT check Possible LOBAT check 3200sps data setting Receiver control line setting example #2 1600sps data or 3200sps data or last used warm up setting Possible LOBAT check 1600sps sync setting Possible LOBAT check 1600sps data setting Figure 14: Examples of Receiver Control Transitions LOW BATTERY DETECTION The S5T8701 can be configured to poll the LOBAT input pin at the end of every receiver control setting. This check can be enabled or disabled for each receiver control setting. If the poll is enabled for a setting, the pin will be read just before the S5T8701 changes the receiver control lines from that setting to another setting. The S5T8701 will send a Status Packet whenever the value on two consecutive reads of the LOBAT pin yields different results. 55 FLEX TM ROAMING DECODER II S5T8701 MESSAGE BUILDING A simple message consists of an Address Packet followed by a Vector Packet indicating the word numbers of associated Message Packets. The tables below show a more complex example of receiving three Messages and two Block Information Word Packets in the first two blocks of a 2 phase 3200bps, FLEX frame. Note that the messages shown may be portions of fragmented or group messages. Note further that in the case of a 6400bps FLEX signal, there would be four phases: A, B, C and D, and in the case of a 1600bps signal there would be only a single phase A. Table 30 on page 59 shows the block number, word number (WN) and word content of both phases A and C. Note contents of words not meant to be received by the host are left blank. Each phase begins with a block information word (WN 0), this is not sent to the host. The first message is in phase A and has an address (WN 3), vector (WN 7) and three message words (WN 9- 11). The second message is also in phase A and has an address (WN 4), a vector (WN 8) and four message words (WN 12 - 15). The third message is in phase C and has a 2 word long address (WN 5 - 6) followed by a vector (WN 10) and three message words. Since the third message is sent on a long address, the first message word (WN 11) begins immediately after the vector. The vector indicates the location of the second and third message words (WN 14 - 15). Table 30: FLEX SIGNAL BLOCK Word Number 0 1 3 0 4 5 6 7 8 9 10 1 11 12 13 14 15 VECTOR 1 VECTOR 2 MESSAGE 1,1 MESSAGE 1,2 MESSAGE 1,3 MESSAGE 2,1 MESSAGE 2,2 MESSAGE 2,3 MESSAGE 2,4 MESSAGE 3,2 MESSAGE 3,3 VECTOR 3 MESSAGE 3,1 ADDRESS 1 ADDRESS 2 LONG ADDRESS 3 WORD 1 LONG ADDRESS 3 WORD 2 PHASE A BIW 1 PHASE C BIW 1 BIW BIW 56 S5T8701 FLEX TM ROAMING DECODER II Table 31 on page 60 shows the sequence of packets received by the host. The S5T8701 processes the FLEX signal one block at a time, and one phase at a time. Thus, the address and vector information in block 0 phase A is sent to the host in packets 1 - 3. Then information in block 0 phase C, two block information words and one long address, is sent to the host in packets 4-6. Packets 7 - 18 correspond to information in block 1, processed in phase A first and phase C second. Table 31: FLEX DECODER PACKET SEQUENCE PACKET 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th 15th 16th 17th PACKET TYPE ADDRESS ADDRESS VECTOR BIW BIW LONG ADDRESS VECTOR MESSAGE MESSAGE MESSAGE MESSAGE MESSAGE MESSAGE MESSAGE VECTOR MESSAGE MESSAGE PHASE A A A C C C A A A A A A A A C C C WORD NUMBER N.A. (7) N.A. (8) 7 N.A. N.A. N.A. (10) 8 9 10 11 12 13 14 15 10 11 14 COMMENT Address 1 has a vector located at WN 7 Address 2 has a vector located at WN 8 Vector for Address 1: Message Words located at WN =9 to 11, phase A If BIWs enabled, then BIW packet sent If BIWs enabled, then BIW packet sent Long Address 3 has a vector beginning in word 10 of phase C Vector for Address 2: Message Words located at WN = 12 to 15, phase A Message information for Address 1 Message information for Address 1 Message information for Address 1 Message information for Address 2 Message information for Address 2 Message information for Address 2 Message information for Address 2 Vector for Long Address 3: Message Words located at WN = 14 - 15, phase C Second word of Long Vector is first message information word of Address 3 Message information for Address 3 18th MESSAGE C 15 Message information for Address 3 The first message is built by relating packets 1, 3, and 8 - 10. The second message is built by relating packets 2, 7 and 11 - 14. The third message is built by relating packets 6 and 15 - 18. Additionally, the host may process block information in packets 4 and 5 for time setting information. 57 FLEX TM ROAMING DECODER II S5T8701 BUILDING A FRAGMENTED MESSAGE The longest message which will fit into a frame is 84 code words total of message data. Three alpha characters per word yields a maximum message of 252 characters in a frame assuming no other traffic. Messages longer than this value must be sent as several fragments. Additional fragments can be expected when the "continue bit" in the 1st Message Word is set. This causes the pager to examine every following frame for an additional fragment until the last fragment with the continue bit reset is found. The only requirement relating to the placement in time of the remaining fragments is that no more than 32 frames (1 minute) or 128 frames (4 minutes) as indicated by the service provider may pass between fragment receptions. Each fragment contains a check sum character to detect errors in the fragment, a fragment number 0, 1, or 2 to detect missing fragments, a message number to identify which message the fragment is a part, and the continue bit which either indicates that more fragments are in queue or that the last fragment has been received. The following describes the sequence of events between the Host and the S5T8701 required to handle a fragmented message: The host will receive a vector indicating one of the following types: V2 V1 V0 000 101 110 * * Type Secure Alphanumeric Hex / Binary The S5T8701 will increment the all frame mode counter inside the S5T8701 and begin to decode all of the following frames. The host will receive the Message Packet(s) contained within that frame followed by a Status Packet. The host must decide based on the Message Packet to return to normal decoding operation. If the message is indicated as fragmented by the Message Continued Flag "C" being set in the Message Packet then the host does not decrement the all frame mode counter at this time. The host decrements the counter if the Message Continued Flag "C" is clear by writing the All Frame Mode Packet to the S5T8701 with the "DAF" bit = 1. If no other fragments, temporary addresses are pending and the FAF bit is clear in the All Frame Mode Register, then the S5T8701 returns to normal operation. The S5T8701 continues to decode all of the frames and passes any address information, vector information and message information to the host followed by a status packet indicating the end of the frame. If the message is indicated as fragmented by the Message Continued Flag "C" in the Message Packet then the host remains in the receive mode expecting more information from the S5T8701. After the host receives the second and subsequent fragment with the Message Continued Flag "C" = 1, it should decrement the all frame mode counter by sending an All Frame Mode Packet to the S5T8701 with the "DAF" bit = 1. Alternatively, the host may choose to decrement the counter at the end of the entire message by decrementing the counter once for each fragment received. * * 58 S5T8701 FLEX TM ROAMING DECODER II * When the host receives a Message Packet with the Message Continued Flag "C" = 0, it will send two All Frame Mode Packets to the S5T8701 with the "DAF" bit = 1. The two packets decrement the count for the first fragment and the last fragment. This decrements the all frame counter to zero, if no other fragmented messages, temporary addresses are pending and the FAF bit is clear in the All Frame Mode Register, the S5T8701 returns to normal operation. The above process must be repeated for each occurrence of a fragmented message. The host must keep track of the number of fragmented messages being decoded and insure the all frame mode counter decrements after each fragment or after each fragmented message. Table 32: Alphanumeric Message without fragmentation PACKET 1st 2nd 3rd 4th PACKET TYPE ADDRESS 1 VECTOR 1 MESSAGE Variablea PHASE A A A All Frame Counter 0 1 1 0 COMMENT Address 1 is received Vector = Alphanumeric Type Message Word received "C" bit = 0, No more fragments are expected. Host writes All Frame Mode Packet to the S5T8701 with the "DAF" bit = 1 * a. Host Initiated Packet. The S5T8701 returns a packet according to "Decoder-to-Host Packet Descriptions" on page 38. Table 33: Alphanumeric Message with fragmentation PACKET 1st 2nd 3rd 4th 5th 6th 7th 8th 9th PACKET TYPE ADDRESS 1 VECTOR 1 MESSAGE STATUS ADDRESS 1 VECTOR 1 MESSAGE Variablea STATUS PHASE A A A All Frame Counter 0 1 1 1 COMMENT Address 1 is received Vector = Alphanumeric Type Message Word received "C" bit = 1, Message is fragmented, more expected End of Frame Indication (EOF = 1) Address 1 is received Vector = Alphanumeric Type Message Word received "C" bit = 1, Message is fragmented, more expected. Host writes All Frame Mode Packet to the S5T8701 with the "DAF" bit = 1 End of Frame Indication (EOF = 1 ) B B B 1 2 2 1 1 59 FLEX TM ROAMING DECODER II S5T8701 Table 33: Alphanumeric Message with fragmentation (Continued) PACKET 10th 11th 12th 13th 14th PACKET TYPE ADDRESS 1 VECTOR 1 MESSAGE Variablea Variablea PHASE A A A All Frame Counter 1 2 2 1 0 COMMENT Address 1 is received Vector = Alphanumeric type Message Word received "C" bit = 0, No more fragments are expected. Host writes All Frame Mode Packet to the S5T8701 with the "DAF" bit = 1 Host writes All Frame Mode Packet to the S5T8701 with the "DAF" bit = 1 a. Host Initiated Packet. The S5T8701 returns a packet according to "Decoder-to Host Packet Descriptions" on page 38. 60 S5T8701 FLEX TM ROAMING DECODER II OPERATION OF A TEMPORARY ADDRESS Group Messaging The FLEX protocol allows for a dynamic group call for the purpose of sending a common message to a group of paging devices. The dynamic group call approach assigns a "Temporary Address" using the personal address and the short instruction vector. The FLEX protocol specifies sixteen addresses for the dynamic group call which may be temporarily activated in a future frame (If the frame or one of the frames designated is equal to the present frame the host is to interpret this as the next occurrence of this frame 4 minutes in the future.) The temporary address is valid for one message starting in the specified frame(s) and remaining valid throughout the following frames to the completion of the message. If the message is not found in the specified frame(s) the host must disable the assigned temporary address. The following describes the sequence of events between the Host and the S5T8701 required to handle a temporary address: * Following an Address Packet, the host will receive a Vector Packet with V2V1V0 = 001 and i2i1i0 = 000 or 010 (a Short Instruction Vector indicating a temporary address has been assigned to this pager). The system may send either i2i1i0 = 000 or i2i1i0 = 010 or both when assigning a temporary address. The vector packet with i2i1i0 = 000 will indicate which temporary address is assigned and the frame in which the temporary address is expected. The vector packet with i2i1i0 =010 will indicate which temporary address is assigned, the MSb of the expected frame (essentially indicating 64 frames in which to look for the temporary address), and a message sequence number. When the vector packet with i2i1i0 = 010 is received on a long address, the specific assign frame is included in the message word sent after the vector The S5T8701 will increment the corresponding temporary address counter for each temporary address assignment vector received and begin to decode all of the following frames. Note that this implies a single dynamic group assignment that is implemented by sending two short instructions ( one for each temporary address assignment mode of the short instruction vector) will cause the corresponding temporary address counter to increment twice. The S5T8701 continues to decode all of the frames and passes any address information, vector information and message information to the host followed by a status packet indicating the end of each frame and the current frame number. There are several scenarios which may occur with temporary addresses 1. The temporary address is not found in the any of the assigned frames and therefore the host must terminate the temporary address mode by sending an All Frame Mode Packet to the S5T8701 with the "DTA" bit of the particular temporary address set. (if both temporary address assignment packets were used to assign the temporary address, the "DTA" bit must be set twice to disable the temporary address) The temporary address is found in the frame it was assigned and was not a fragmented message. Again, the host must terminate the temporary address mode by sending an All Frame Mode Packet to the S5T8701 with the "DTA" bit of the particular temporary address set.(if both temporary address assignment packets were used to assign the temporary address, the "DTA" bit must be set twice to disable the temporary address) * * * 2. 61 FLEX TM ROAMING DECODER II S5T8701 3. The temporary address is found in the assigned frame and it is a fragmented message. In this case, the host must follow the rules for Operation of a Fragmented Message and determine the proper time to stop the all frame mode operation. In this case, the host must write to the "DAF" bit with a "1" and the appropriate "DTA" bit with a "1" in the All Frame Mode Register in order to terminate both the fragmented message and the temporary address. (if both temporary address assignment packets were used to assign the temporary address, the "DTA" bit must be set twice to disable the temporary address) * The above operation is repeated for every temporary address. 62 S5T8701 FLEX TM ROAMING DECODER II USING THE RECEIVER SHUTDOWN PACKET Calculating Time Left The receiver shutdown packet gives timing information to the host. Two times are of particular interest when implementing a roaming algorithm. * * Time To Warm Up Start. Defined as the amount of time there is before the receiver will start to warm up (i.e. transition from the off state to the first warm up state). Time To Tasks Disabled. Defined as the amount of time the host has to complete any host initiated tasks (e.g. by setting SND or SAS in the roaming control packet). The formula's for calculating these times depend on whether the S5T8701 is in synchronous mode or asynchronous mode. SYNCHRONOUS MODE: Time To Warm Up Start (TNF * 80ms) + (Skipped Frames * 1874.375ms) + Receiver Off Time - 167.5ms Time To Tasks Disabled (TNF * 80ms) + (Skipped Frames * 1874.375ms) - 247.5ms ASYNCHRONOUS MODE: Time To Warm Up Start ((TNF - 2) * 80ms) + Receiver Off Time Time To Tasks Disabled ((TNF - 3) * 80ms) Where, TNF: Time to Next Frame. Value from the receiver shutdown packet. Skipped Frames: The number of frames that won't be decoded. This can be calculated from the Current Frame (CF) and Next Needed Frame (NAF) fields in the receiver shutdown packet (e.g. If CF is 10 and NAF is 12, then Skipped Frames is 1) Receiver Off Time: The time programmed in the receiver off setting packet. 63 FLEX TM ROAMING DECODER II S5T8701 Calculating How Long Tasks Take Since the Time To Task Disabled discussed in the previous section limits how much the host can do while the S5T8701 is battery saving, it is necessary for the host to know how long it can take the S5T8701 to perform a task. The formulas below calculate how long the two types of host initiated tasks take to complete as measured from the last SPI clock of the packet that initiates the task to the time the receiver shutdown sequence starts. Note that the receiver shutdown sequence must start before tasks are disabled. The following formula calculates how long it will take to complete a Noise Detect started by setting the SND bit in the roaming control packet. This formula assumes that (1) the noise detect was performed while in synchronous mode or (2) the noise detect was performed in asynchronous mode and did not find FLEX signal or (3) the noise detect found FLEX signal but the DAS bit of the roaming control packet was set. Time To Perform Noise Detect -- Total Warm Up Time + 82ms Where, Total Warm Up Time: The sum of the times programmed for the used warm up steps plus the time programmed for the 3200sps Sync Setting in the receiver control configuration packets. The following formula calculates how long it will take to complete an A-word search initiated by setting the SAS bit in the roaming control packet. This formula assumes that the A-word search failed to find roaming FLEX channel. Time To Perform A word Search -- Total Warm Up Time + AST + 47ms Where, Total Warm Up Time: The sum of the times programmed for the used warm up steps plus the time programmed for the 3200sps Sync Setting in the receiver control configuration packets. AST: The value configured using the timing control packet. The following formula calculates how long it will take to complete a Noise Detect/A-word search combination. This can occur when the noise detect is performed while in asynchronous mode, the noise detect finds FLEX signal, and the DAS bit of the roaming control packet is not set. Time To Perform Both -- Total Warm Up Time + AST + 127ms Where, Total Warm Up Time: The sum of the times programmed for the used warm up steps plus the time programmed for the 3200sps Sync Setting in the receiver control configuration packets. AST: The value configured using the timing control packet. 64 S5T8701 FLEX TM ROAMING DECODER II APPENDIX B: SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Table 34: Absolute Maximum Ratings Characteristic DC Supply Voltage DC Input Voltage DC Input Current Storage Temperature Operating Temperature Symbol VDD VIN IIN TSTG TOPR Min -0.3 -0.3 -10 -40 -25 Max 3.8 VDD + 0.3 +10 +125 +85 Unit V V mA C C Absolute Maximum Ratings may cause critical device failure by above table beyond limits. All electrical characteristics are applied in digital cell library without analog core. DC CHARACTERISTICS Table 35: DC Characteristics Characteristic Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Tri-state Output Leakage Current Standby Supply Current a Input Capacitance b @3V, 76.8kHz, 25C IOH=-1mA IOL=1mA Test Conditions Symbol VDD VIH VIL IIH IIL VOH VOL IOZ IDD CIN -5 18 4 4 -1 -1 VDD-0.4 0.4 5 Min 1.8 0.8VDD 0.2VDD 1 1 Typ 3.0 Max 3.6 Unit V V V A A V V A A pF pF COUT Output Capacitance b a. This value depends on the customer application. b. This value excludes package parasitic capacitance. 65 FLEX TM ROAMING DECODER II S5T8701 AC CHARACTERISTICS SPI Timing The following diagram and table describe the timing specifications of the SPI interface. SS tSSH READY tRDY tLEAD1 tLEAD2 tCYC tR tF tLAG2 tLAG1 tRH SCK tSCKL tSCKH MISO Hi-Z D31 tAC tV D31 tHI tSU tHO D0 tDIS D0 Hi-Z MOSI Figure 15: SPI Timing 66 S5T8701 FLEX TM ROAMING DECODER II Table 36: SPI Timing (VDD = 1.8V to 3.6V, Ta = -25C to +85C) Characteristic Operating Frequency Cycle Time Select Lead Time De-select Lag Time Select-to-Ready Time Select-to-Ready Time Ready High Time Ready Lead Time Not Ready Lag Time MOSI Data Setup Time MOSI Data Hold Time MISO Access Time MISO Disable Time MISO Data Valid Time MISO Data Hold Time SS High Time SCK High Time SCK Low Time SCK Rise Time 20% to 70% VDD CL=50pf CL=50pf CL=50pf previous packet did not program an address word a CL=50pf previous packet programmed an address worda CL=50pf Conditions Symbol f OP tCYC tLEAD1 tLAG1 tRDY tRDY tRH tLEAD2 tLAG2 tSU tHI tAC tDIS tV tHO tSSH tSCKH tSCKL tR 0 200 300 300 1 200 200 0 200 300 200 50 200 200 Min 0 1000 200 200 80 420 Max 1 Unit MHz ns ns ns s s s ns ns ns ns ns ns ns ns ns ns ns s tF SCK Fall Time 20% to 70% VDD 1 s a. When the host re-programs an address word with a Host-to-FLEX decoder packet ID > 127(decimal), there may be an added delay before the S5T8701 is ready for another packet. 67 FLEX TM ROAMING DECODER II S5T8701 START-UP TIMING The following diagram and table describe the timing specifications of the S5T8701 when power is applied. VDD tSTART Oscillator RESET tRESET READY tOWRL tRHRL Figure 16: Start-up Timing Table 37: Start-up Timing (VDD = 1.8V to 3.6V, Ta = -25C to +85C) Characteristic Oscillator Start-up Time RESET Hold Time RESET High to READY Low a Conditions Symbol tSTART tRESET tRHRL 200 1 Min Typ Max 5 Unit sec ns sec CL=50pf tOWRL 1 sec Oscillator Warmed up to READY Low a a. Note that from power-up, the oscillator start-up time can impact the availability and period of clock strobes. This can affect the actual RESET high to READY low timing. 68 S5T8701 FLEX TM ROAMING DECODER II RESET TIMING The following diagram and table describe the timing specifications of the S5T8701 when it is reset. RESET tRL READY tRLRH tRHRL Figure 17: Reset Timing Table 38: Reset Timing (VDD = 1.8V to 3.6V, Ta = -25C to 85C) Characteristic RESET Pulse Width RESET Low to READY High RESET High to READY Low Requires stable clock Conditions Symbol tRL tRLRH tRHRL Min 200 1 Typ Max 200 Unit ns ns sec 69 FLEX TM ROAMING DECODER II S5T8701 MECHANICAL SPECIFICATION PACKAGE DEMENSION 9.00 + 0.30 7.00 + 0.20 0-8 + 0.10 0.127- 0.05 9.00 + 0.30 7.00 + 0.20 0.10 MAX #32 #1 0.80 + 0.10 0.30 - 0.05 (0.70) 0.05 MIN 1.40 + 0.10 1.70 MAX 0.10 MAX Figure 5 : 32-LQFP-0707 Package Dimension 70 0.50 + 0.20 |
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